Method for adjusting the height of a gate electrode in a semiconductor device

Abstract

By providing an implantation blocking material on the gate electrode structures of advanced semiconductor devices during high energy implantation processes, the required shielding effect with respect to the channel regions of the transistors may be accomplished. In a later manufacturing stage, the implantation blocking portion may be removed to reduce the gate electrode height to a desired level in order to enhance the process conditions during the deposition of an interlayer dielectric material, thereby significantly reducing the risk of creating irregularities, such as voids, in the interlayer dielectric material, even in densely packed device regions.

1 . A method, comprising:
 forming a gate electrode structure of a transistor above a semiconductor layer, said gate electrode structure comprising an electrode portion formed on a gate insulation layer and an implantation blocking portion formed on said electrode portion;   forming drain and source regions in said semiconductor layer by ion implantation using said gate electrode structure as an implantation mask to substantially prevent penetration of ions into a channel region of said transistor;   removing at least said implantation blocking portion to expose said electrode portion; and   forming an interlayer dielectric material adjacent and above said electrode portion.   
     
     
         2 . The method of  claim 1 , wherein removing at least said implantation blocking portion comprises performing a polishing process. 
     
     
         3 . The method of  claim 2 , further comprising depositing a planarization material prior to performing said polishing process. 
     
     
         4 . The method of  claim 1 , further comprising forming a metal silicide region in said electrode portion. 
     
     
         5 . The method of  claim 1 , wherein forming said gate electrode structure comprises forming a gate insulation layer and an electrode material on said gate insulation layer and forming at least one further material layer on said electrode material, said at least one further material layer being comprised of a material differing from said electrode material. 
     
     
         6 . The method of  claim 5 , wherein said at least one further material layer is a top layer of said gate electrode structure. 
     
     
         7 . The method of  claim 5 , wherein said at least one further material layer is an intermediate layer followed by one or more additional layers. 
     
     
         8 . The method of  claim 7 , wherein said one or more additional layers are comprised of material substantially corresponding to said electrode material. 
     
     
         9 . The method of  claim 6 , wherein forming said gate electrode structure comprises patterning said implantation blocking portion by a first etch process and using said patterned implantation blocking portion as an etch mask during a second etch process for patterning said electrode portion. 
     
     
         10 . The method of  claim 8 , wherein forming said gate electrode structure comprises performing a first etch step for etching through said implantation blocking portion while using said intermediate layer as an etch stop layer and performing a second etch step for etching through said electrode portion. 
     
     
         11 . The method of  claim 1 , wherein removing said implantation blocking portion comprises performing an etch process. 
     
     
         12 . A method, comprising:
 forming a plurality of gate electrode structures above a semiconductor layer, each of said plurality of gate electrode structures having an initial height;   forming drain and source regions in said semiconductor layer by ion implantation using said plurality of gate electrode structures as an implantation mask, said initial height being selected to substantially prevent penetration of ions in said semiconductor layer;   reducing said initial height of said plurality of gate electrode structures to obtain a reduced height; and   forming an interlayer dielectric material adjacent and above said plurality of gate electrode structures having said reduced height.   
     
     
         13 . The method of  claim 12 , wherein reducing said initial height comprises depositing a planarization material and performing a removal process using said planarization material. 
     
     
         14 . The method of  claim 13 , wherein performing said removal process comprises performing a chemical mechanical polishing process. 
     
     
         15 . The method of  claim 13 , wherein performing said removal process comprises performing an etch process. 
     
     
         16 . The method of  claim 12 , wherein forming said plurality of gate electrode structures comprises forming an electrode material on a gate insulation layer and forming at least one material layer on said electrode material, said electrode material and said at least one material layer defining said initial height. 
     
     
         17 . The method of  claim 16 , wherein said at least one material layer is provided as a single material layer. 
     
     
         18 . The method of  claim 16 , wherein forming said at least one material layer comprises forming an intermediate layer and forming at least one blocking layer on said intermediate layer, said intermediate layer and said at least one blocking layer having different material compositions. 
     
     
         19 . A semiconductor device, comprising:
 a gate electrode structure formed above a semiconductor layer and comprising a gate insulation layer and an electrode portion formed on said gate insulation layer, said electrode portion having a height corresponding to a first amount; and   drain and source regions formed in said semiconductor layer and extending in a depth direction a second amount, said drain and source regions having a top surface at a height level substantially defined by said gate insulation layer, said first amount being less than said second amount.   
     
     
         20 . The semiconductor device of  claim 19 , wherein a length of said gate electrode structure is approximately 50 nm or less.