Inventor · disambiguated record
Kerstin Ruttloff
Also filed as: RUTTLOFF KERSTIN
12 granted patents·3 pending applications·131 citations·filing 2008–2011
87Inventor score
Top patents by PatentIndex Score
15 records- 0197US8110487B2Method of creating a strained channel region in a transistor by deep implantation of strain-inducing species below the channel regionGRIEBENOW UWE·Filed 2008·Granted Feb 7, 2012·104 cites·20 claims
- 0288US7981740B2Enhanced cap layer integrity in a high-K metal gate stack by using a hard mask for offset spacer patterningGLOBALFOUNDRIES INC·Filed 2010·Granted Jul 19, 2011·13 cites·21 claims
- 0374US8318598B2Contacts and vias of a semiconductor device formed by a hard mask and double exposureBEYER SVEN·Filed 2009·Granted Nov 27, 2012·6 cites·25 claims
- 0470US8440534B2Threshold adjustment for MOS devices by adapting a spacer width prior to implantationGRIEBENOW UWE·Filed 2011·Granted May 14, 2013·2 cites·17 claims
- 0566US8709902B2Sacrificial spacer approach for differential source/drain implantation spacers in transistors comprising a high-k metal gate electrode structureSCHEIPER THILO·Filed 2011·Granted Apr 29, 2014·2 cites·24 claims
- 0658US8436425B2SOI semiconductor device comprising substrate diodes having a topography tolerant contact structureHEINRICH JENS·Filed 2010·Granted May 7, 2013·1 cites·20 claims
- 0757US8039338B2Method for reducing defects of gate of CMOS devices during cleaning processes by modifying a parasitic PN junctionGLOBALFOUNDRIES INC·Filed 2009·Granted Oct 18, 2011·1 cites·9 claims
- 0855US8097542B2Etch stop layer of reduced thickness for patterning a dielectric material in a contact level of closely spaced transistorsWIECZOREK KARSTEN·Filed 2008·Granted Jan 17, 2012·2 cites·20 claims
- 0954US2009321850A1Threshold adjustment for MOS devices by adapting a spacer width prior to implantationGRIEBENOW UWE·Filed 2009·Application pending·0 cites
- 1044US2009294868A1Drive current adjustment for transistors formed in the same active region by locally inducing different lateral strain levels in the active regionGRIEBENOW UWE·Filed 2009·Application pending·0 cites
- 1144US2010025782A1Technique for reducing silicide non-uniformities in polysilicon gate electrodes by an intermediate diffusion blocking layerGRIEBENOW UWE·Filed 2009·Application pending·0 cites
- 1243US8188871B2Drive current adjustment for transistors by local gate engineeringHORSTMANN MANFRED·Filed 2009·Granted May 29, 2012·0 cites·26 claims
- 1339US8772843B2Oxide deposition by using a double liner approach for reducing pattern density dependence in sophisticated semiconductor devicesKRONHOLZ STEPHAN·Filed 2011·Granted Jul 8, 2014·0 cites·30 claims
- 1439US8048726B2SOI semiconductor device with reduced topography above a substrate window areaGLOBALFOUNDRIES INC·Filed 2010·Granted Nov 1, 2011·0 cites·21 claims
- 1534US8987103B2Multi-step deposition of a spacer material for reducing void formation in a dielectric material of a contact level of a semiconductor deviceLENSKI MARKUS·Filed 2010·Granted Mar 24, 2015·0 cites·21 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →