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MOSYS INC

US47 patents

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US5784705AJul 21, 1998

Method and structure for performing pipeline burst accesses in a semiconductor memory

MOSYS INC147 citations98
US7634707B2Dec 15, 2009

Error detection/correction method

MOSYS INC12 citations93
US7533222B2May 12, 2009

Dual-port SRAM memory using single-port memory cell

MOSYS INC28 citations93
US7447104B2Nov 4, 2008

Word line driver for DRAM embedded in a logic process

MOSYS INC40 citations93
US6259651B1Jul 10, 2001

Method for generating a clock phase signal for controlling operation of a DRAM array

MOSYS INC17 citations93
US7671401B2Mar 2, 2010

Non-volatile memory in CMOS logic process

MOSYS INC35 citations92
US7633810B2Dec 15, 2009

Non-volatile memory embedded in a conventional logic process and methods for operating same

MOSYS INC14 citations92
US7391647B2Jun 24, 2008

Non-volatile memory in CMOS logic process and method of operation thereof

MOSYS INC36 citations92
US7392456B2Jun 24, 2008

Predictive error correction code generation facilitating high-speed byte-write in a semiconductor memory

MOSYS INC34 citations92
US8044724B2Oct 25, 2011

Low jitter large frequency tuning LC PLL for multi-speed clocking applications

MOSYS INC46 citations90
US7353438B2Apr 1, 2008

Transparent error correcting memory

MOSYS INC39 citations89
US10114558B2Oct 30, 2018

Integrated main memory and coprocessor with low latency

MOSYS INC7 citations84
US7929359B2Apr 19, 2011

Embedded DRAM with bias-independent capacitance

MOSYS INC8 citations84
US7323379B2Jan 29, 2008

Fabrication process for increased capacitance in an embedded DRAM memory

MOSYS INC18 citations84
US9361196B2Jun 7, 2016

Memory device with background built-in self-repair using background built-in self-testing

MOSYS INC9 citations83
US7633811B2Dec 15, 2009

Non-volatile memory embedded in a conventional logic process and methods for operating same

MOSYS INC8 citations83
US9054578B2Jun 9, 2015

Hybrid driver including a turbo mode

MOSYS INC8 citations81
US7499307B2Mar 3, 2009

Scalable embedded DRAM array

MOSYS INC5 citations74
US6147535ANov 14, 2000

Clock phase generator for controlling operation of a DRAM array

MOSYS INC12 citations74
US6078547AJun 20, 2000

Method and structure for controlling operation of a DRAM array

MOSYS INC9 citations74
US10339043B1Jul 2, 2019

System and method to match vectors using mask and count

MOSYS INC2 citations73
US9354823B2May 31, 2016

Memory system including variable write burst and broadcast command scheduling

MOSYS INC3 citations73
US8988956B2Mar 24, 2015

Programmable memory built in self repair circuit

MOSYS INC4 citations73
US7894270B2Feb 22, 2011

Data restoration method for a non-volatile memory

MOSYS INC6 citations73
US7477546B2Jan 13, 2009

Non-volatile memory embedded in a conventional logic process and methods for operating same

MOSYS INC4 citations73
US7382658B2Jun 3, 2008

Non-volatile memory embedded in a conventional logic process and methods for operating same

MOSYS INC7 citations73
US9148154B2Sep 29, 2015

Delay-locked loop with independent phase adjustment of delayed clock output pairs

MOSYS INC4 citations72
US8836381B2Sep 16, 2014

Pseudo-supply hybrid driver

MOSYS INC5 citations72
US10320370B2Jun 11, 2019

Methods and circuits for adjusting parameters of a transceiver

MOSYS INC4 citations71
US7791975B2Sep 7, 2010

Scalable embedded DRAM array

MOSYS INC1 citations63
US7684229B2Mar 23, 2010

Scalable embedded DRAM array

MOSYS INC4 citations63
US9529569B2Dec 27, 2016

Method and apparatus for randomizer

MOSYS INC2 citations62
US8361863B2Jan 29, 2013

Embedded DRAM with multiple gate oxide thicknesses

MOSYS INC3 citations62
US7522456B2Apr 21, 2009

Non-volatile memory embedded in a conventional logic process and methods for operating same

MOSYS INC2 citations62
US9496009B2Nov 15, 2016

Memory with bank-conflict-resolution (BCR) module including cache

MOSYS INC2 citations60
US8368217B2Feb 5, 2013

Integrated circuit package with segregated Tx and Rx data channels

MOSYS INC2 citations59
US9030894B2May 12, 2015

Hierarchical multi-bank multi-port memory organization

MOSYS INC2 citations56
US7944281B2May 17, 2011

Constant reference cell current generator for non-volatile memories

MOSYS INC3 citations54
US10050773B1Aug 14, 2018

Bootstrapped autonegotiation clock from a referenceless clock chip

MOSYS INC0 citations52
US9971567B2May 15, 2018

Method and apparatus for randomizer

MOSYS INC0 citations52
US9921755B2Mar 20, 2018

Integrated main memory and coprocessor with low latency

MOSYS INC0 citations52
US9553566B2Jan 24, 2017

Hybrid driver circuit

MOSYS INC1 citations52
US9667546B2May 30, 2017

Programmable partitionable counter

MOSYS INC0 citations51
US7919367B2Apr 5, 2011

Method to increase charge retention of non-volatile memory manufactured in a single-gate logic process

MOSYS INC1 citations51
US8370725B2Feb 5, 2013

Communication interface and protocol

MOSYS INC1 citations48
US7728747B2Jun 1, 2010

Comparator chain offset reduction

MOSYS INC1 citations43
US10084488B1Sep 25, 2018

Chip-to-chip port coherency without overhead

MOSYS INC0 citations31