Processing engines coupled with read write modify memory

Abstract

System, method, and apparatus for integrated main memory (MM) and configurable coprocessor (CP) chip for processing subset of network functions. Chip supports external accesses to MM without additional latency from on-chip CP. On-chip memory scheduler resolves all bank conflicts and configurably load balances MM accesses. Instruction set and data on which the CP executes instructions are all disposed on-chip with no on-chip cache memory, thereby avoiding latency and coherency issues. Multiple independent and orthogonal threading domains used: a FIFO-based scheduling domain (SD) for the I/O; a multi-threaded processing domain for the CP. The CP is an array of independent, autonomous, unsequenced processing engines processing on-chip data tracked by SD of external CMD and reordered per FIFO CMD sequence before transmission. Paired I/O ports tied to unique global on-chip SD allow multiple external processors to slave chip and its resources independently and autonomously without scheduling between the external processors.

Me claim: 
     
         1 . A network system comprising:
 a packet forwarding engines (PFE); and   an IC coupled to the PFE, wherein the IC comprises:
 a main memory (MM) comprising:
 a plurality of memory cells configured to store the data; 
 a memory controller (MC); and 
 
 a coprocessor CP coupled to the MM, the coprocessor comprising:
 a processing engine (PE) coupled to the MM; and wherein:
 the PFE is configured to send a command to the IC consisting of: an access CMD to MM, or a CSUB CMD to the CP. 
 
 
   
     
     
         2 . The network system of  claim 1  wherein:
 the PFE sends a CMD to the IC to execute an EXACT MATCH or a LEAST PREFIX MATCH operation using the CP; and 
 the PFE sends a CMD to the IC to execute a READ, a WRITE, or a READ/MODIFY/WRITE (RMW) to access data on the MM of the IC; and 
 the data is not cached from an external memory.