Inventor · disambiguated record
Michael J. Morrison
Also filed as: MORRISON MICHAEL · MORRISON MICHAEL J · MORRISON MICHAEL JAMES
32 granted patents·1 pending application·722 citations·filing 1996–2018
97Inventor score
Top patents by PatentIndex Score
33 records- 0192US10114558B2Integrated main memory and coprocessor with low latencyMOSYS INC·Filed 2018·Granted Oct 30, 2018·7 cites·20 claims
- 0286US8635417B2Memory system including variable write command schedulingMORRISON MICHAEL J·Filed 2012·Granted Jan 21, 2014·9 cites·28 claims
- 0386US6151669AMethods and apparatus for efficient control of floating-point status registerINST THE DEV OF EMERGING ARCHI·Filed 1998·Granted Nov 21, 2000·122 cites·31 claims
- 0482US8832336B2Reducing latency in serializer-deserializer linksMORRISON MICHAEL J·Filed 2010·Granted Sep 9, 2014·5 cites·23 claims
- 0579US8527676B2Reducing latency in serializer-deserializer linksMORRISON MICHAEL J·Filed 2012·Granted Sep 3, 2013·6 cites·20 claims
- 0677US9529569B2Method and apparatus for randomizerMOSYS INC·Filed 2015·Granted Dec 27, 2016·2 cites·20 claims
- 0775US5961630AMethod and apparatus for handling dynamic structural hazards and exceptions by using post-ready latencyINTEL CORP·Filed 1997·Granted Oct 5, 1999·70 cites·21 claims
- 0873US9354823B2Memory system including variable write burst and broadcast command schedulingMOSYS INC·Filed 2013·Granted May 31, 2016·3 cites·43 claims
- 0972US11221764B2Partitioned memory with shared memory resources and configurable functionsMILLER MICHAEL J·Filed 2014·Granted Jan 11, 2022·3 cites·25 claims
- 1072US6301705B1System and method for deferring exceptions generated during speculative executionINST THE DEV OF EMERGING ARCHI·Filed 1998·Granted Oct 9, 2001·59 cites·17 claims
- 1172US5880985AEfficient combined array for 2n bit n bit multiplicationsINTEL CORP·Filed 1996·Granted Mar 9, 1999·65 cites·16 claims
- 1268US8473695B2Memory system including variable write command schedulingMORRISON MICHAEL J·Filed 2011·Granted Jun 25, 2013·2 cites·22 claims
- 1365US6249798B1Method, apparatus and computer system for directly transferring and translating data between an integer processing unit and a floating point processing unitINST THE DEV OF EMERGING ARCHI·Filed 1996·Granted Jun 19, 2001·26 cites·30 claims
- 1465US6223278B1Method and apparatus for floating point (FP) status word handling in an out-of-order (000) Processor PipelineINTEL CORP·Filed 1998·Granted Apr 24, 2001·46 cites·23 claims
- 1565US5996064AMethod and apparatus for guaranteeing minimum variable schedule distance by using post-ready latencyINTEL CORP·Filed 1997·Granted Nov 30, 1999·44 cites·22 claims
- 1660US6279102B1Method and apparatus employing a single table for renaming more than one class of registerINTEL CORP·Filed 1997·Granted Aug 21, 2001·36 cites·19 claims
- 1760US6170052B1Method and apparatus for implementing predicated sequences in a processor with renamingINTEL CORP·Filed 1997·Granted Jan 2, 2001·36 cites·34 claims
- 1859US2019332274A1Processing engines coupled with read write modify memoryMOSYS INC·Filed 2018·Application pending·0 cites
- 1957US8370725B2Communication interface and protocolMOSYS INC·Filed 2010·Granted Feb 5, 2013·1 cites·27 claims
- 2056US9971567B2Method and apparatus for randomizerMOSYS INC·Filed 2016·Granted May 15, 2018·0 cites·20 claims
- 2155US9921755B2Integrated main memory and coprocessor with low latencyMOSYS INC·Filed 2015·Granted Mar 20, 2018·0 cites·20 claims
- 2255US5918031AComputer utilizing special micro-operations for encoding of multiple variant code flowsINTEL CORP·Filed 1996·Granted Jun 29, 1999·34 cites·25 claims
- 2352US9667546B2Programmable partitionable counterMOSYS INC·Filed 2013·Granted May 30, 2017·0 cites·23 claims
- 2452US5848256AMethod and apparatus for address disambiguation using address component identifiersINST THE DEV OF EMERGING ARCHI·Filed 1996·Granted Dec 8, 1998·25 cites·19 claims
- 2550US6370639B1Processor architecture having two or more floating-point status fieldsINST THE DEV OF EMERGING ARCHI·Filed 1998·Granted Apr 9, 2002·23 cites·43 claims
- 2650US6094713AMethod and apparatus for detecting address range overlapsINTEL CORP·Filed 1997·Granted Jul 25, 2000·24 cites·25 claims
- 2748US6578059B1Methods and apparatus for controlling exponent range in floating-point calculationsINST THE DEV OF EMERGING ARCHI·Filed 1998·Granted Jun 10, 2003·20 cites·22 claims
- 2848US6412067B1Backing out of a processor architectural stateINTEL CORP·Filed 1998·Granted Jun 25, 2002·21 cites·42 claims
- 2941US6212539B1Methods and apparatus for handling and storing bi-endian words in a floating-point processorINST THE DEV OF EMERGING ARCHI·Filed 1998·Granted Apr 3, 2001·13 cites·14 claims
- 3035US5961615AMethod and apparatus for queuing dataINTEL CORP·Filed 1997·Granted Oct 5, 1999·8 cites·14 claims
- 3135US5954814ASystem for using a branch prediction unit to achieve serialization by forcing a branch misprediction to flush a pipelineINTEL CORP·Filed 1997·Granted Sep 21, 1999·7 cites·12 claims
- 3231US6216221B1Method and apparatus for expanding instructionsINTEL CORP·Filed 1997·Granted Apr 10, 2001·4 cites·29 claims
- 3330US6021486AContinued processing of out-of-order non-architectual operations upon exceptions until flushing by architectual operations exceptions to avoid resume deadlockINTEL CORP·Filed 1997·Granted Feb 1, 2000·1 cites·16 claims
Join the waitlist — get patent alerts
Get an alert when Michael J. Morrison files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →