Assignee
SPERBER ZEEV
IL·8 granted patents·4 pending applications·83 citations·filing 2005–2012
Technology mixG06F12
Top patents by PatentIndex Score
12 records- 0196US8914613B2Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a same set of per-lane control bitsSPERBER ZEEV·Filed 2011·Granted Dec 16, 2014·22 cites·27 claims
- 0293US8078836B2Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a common set of per-lane control bitsSPERBER ZEEV·Filed 2007·Granted Dec 13, 2011·21 cites·37 claims
- 0392US8972697B2Gather using index array and finite state machineSPERBER ZEEV·Filed 2012·Granted Mar 3, 2015·17 cites·26 claims
- 0480US8103858B2Efficient parallel floating point exception handling in a processorSPERBER ZEEV·Filed 2008·Granted Jan 24, 2012·14 cites·15 claims
- 0578US9626333B2Scatter using index array and finite state machineSPERBER ZEEV·Filed 2012·Granted Apr 18, 2017·5 cites·22 claims
- 0673US8909988B2Recoverable parity and residue errorSPERBER ZEEV·Filed 2012·Granted Dec 9, 2014·3 cites·24 claims
- 0761US8706789B2Performing reciprocal instructions with high accuracySPERBER ZEEV·Filed 2010·Granted Apr 22, 2014·1 cites·16 claims
- 0846US9092226B2Efficient parallel floating point exception handling in a processorSPERBER ZEEV·Filed 2011·Granted Jul 28, 2015·0 cites·11 claims
- 0945US2009327657A1GENERATING AND PERFORMING DEPENDENCY CONTROLLED FLOW COMPRISING MULTIPLE MICRO-OPERATIONS (uops)SPERBER ZEEV·Filed 2008·Application pending·0 cites
- 1044US2009327661A1Mechanisms to handle free physical register identifiers for smt out-of-order processorsSPERBER ZEEV·Filed 2008·Application pending·0 cites
- 1143US2007088965A1Processor and methods to reduce power consumption of processor componentsSPERBER ZEEV·Filed 2006·Application pending·0 cites
- 1241US2007005940A1System, apparatus and method of executing a micro operationSPERBER ZEEV·Filed 2005·Application pending·0 cites
Counts cover granted patents and pending applications in the PatentIndex corpus. How scoring works →