Processor and methods to reduce power consumption of processor components

Abstract

Periods of futile activity by one or more logic circuits of a component of a processor may be predicted, and then during each such period, one or more of the logic circuits may operate in a power-save state with reduced power consumption, with the latter part of the period being used to bring the logic circuits back into performance state, so that performance is not diminished beyond an acceptable level due to the power-save state. The decision of whether to reduce the power consumption of a particular logic circuit of a particular processor component is to have at a particular future time is made internally in the particular processor component based on one or more signals received by the particular processor component.

1 . A method comprising: 
 determining that a logic block within a microprocessor is not presently able to perform an operation; and    placing the logic block in a low power state.    
   
   
       2 . The method of  claim 1 , further comprising monitoring at least one signal to determine a future time when the logic block will be able to perform the operation, and at the future time, placing the logic block in a performance state.  
   
   
       3 . The method of  claim 2 , further comprising placing at least one sub-block within the logic block in a powered state before placing the logic block in the performance state.  
   
   
       4 . The method of  claim 3 , wherein the at least one sub-block is a counter.  
   
   
       5 . The method of  claim 2 , wherein the logic block is a dispatch logic block.  
   
   
       6 . The method of  claim 5 , wherein the operation is dispatching of at least one micro-operation.  
   
   
       7 . The method of  claim 5 , wherein determining that the dispatch logic block is not presently able to perform an operation comprises determining that there are no micro-operations valid to dispatch.  
   
   
       8 . The method of  claim 7 , wherein determining that the dispatch logic block is not presently able to perform the operation further comprises determining that there are no fast micro-operations in progress.  
   
   
       9 . The method of  claim 5 , wherein monitoring at least one signal to determine a future time when the dispatch logic block will be able to perform the operation comprises receiving a completion indication for a slow micro-operation.  
   
   
       10 . The method of  claim 9 , wherein monitoring at least one signal to determine a future time when the dispatch logic block will be able to perform the operation further comprises receiving a valid for dispatching micro-operation.  
   
   
       11 . The method of  claim 2 , wherein the logic block is a retire logic block.  
   
   
       12 . The method of  claim 11 , wherein the operation is retiring at least one micro-operation.  
   
   
       13 . The method of  claim 11 , wherein determining that the retire logic block is not presently able to perform the operation comprises determining that there are no valid for retiring micro-operations.  
   
   
       14 . The method of  claim 13 , wherein determining that the retire logic block is not presently able to perform an operation further comprises determining that a write back bus does not have data intended for a next micro-operation.  
   
   
       15 . The method of  claim 11 , wherein monitoring at least one signal to determine a future time when the retire logic block will be able to perform the operation comprises receiving an identification number associated with a next micro-operation to be retired according to an original order of micro-operations.  
   
   
       16 . An apparatus, comprising: 
 a logic block; and    control circuitry coupled to the logic block, the control circuitry to determine when the logic block is unable to perform an operation and to subsequently place the logic block in a low power state.    
   
   
       17 . The apparatus of  claim 16 , wherein the control circuitry is further to monitor at least one signal to determine a time when the logic block is able to perform an operation, and at that time, to place the logic block in a performance state.  
   
   
       18 . The apparatus of  claim 17 , wherein the at least one signal is a signal to be provided by an execution unit coupled to the logic block and to the control circuitry.  
   
   
       19 . The apparatus of  claim 17 , wherein the control circuitry is further to place at least one sub-block within the logic block in a powered state prior to the time when the logic block is able to perform an operation.  
   
   
       20 . The apparatus of  claim 19 , wherein the at least one sub-block is a counter.  
   
   
       21 . The apparatus of  claim 16 , wherein the logic block is a dispatch logic block and the operation is a dispatch operation.  
   
   
       22 . The apparatus of  claim 16 , wherein the logic block is a retire logic block and the operation is a retire operation.