GENERATING AND PERFORMING DEPENDENCY CONTROLLED FLOW COMPRISING MULTIPLE MICRO-OPERATIONS (uops)

Abstract

A processor to perform an out-of-order (OOO) processing in which a reservation station (RS) may generate and process a dependency controlled flow comprising multiple micro-operations (uops) with specific clock based dispatch scheme. The RS may either combine two or more uops into a single RS entry or make a direct connection between two or more RS entries. The RS may allow more than two source values to be associated with a single RS by combining sources from the two or more uops. One or more execution units may be provisioned to perform the function defined by the uops. The execution units may receive more than two sources at a given time point and produce two or more results on different ports.

1 . A method comprising:
 receiving a plurality of micro-operations representing an instruction;   generating a dependency controlled flow using the plurality of micro-operations in a reservation station of an out-of-order execution block, wherein the dependency between a first micro-operation and a second micro-operation of the plurality of micro-operations established by the dependency controlled flow ensures that the second micro-operation is dispatched after a specific delay after dispatching the first micro-operation; and   generating a plurality of results in an execution block using a plurality of source values received from the reservation station, wherein the plurality of results are provided over a plurality of ports of the reservation station.   
     
     
         2 . The method of  claim 1 , wherein the dependency controlled flow is to map a combination of the first micro-operation and the second micro-operation of the plurality of micro-operations into a single reservation station entry, wherein a first set of source values associated with the first micro-operation and a second set of source values associated with the second micro-operation is associated with the single reservation station entry. 
     
     
         3 . The method of  claim 1 , wherein the dependency controlled flow is to assert a line after dispatching a first reservation station entry, wherein the asserted line is to ensure dispatch of the second reservation station entry that is ready, wherein the second reservation station entry is dispatched after a specific delay after the first reservation station entry is dispatched. 
     
     
         4 . The method of  claim 3 , wherein the dependency controlled flow comprising the first micro-operation and the second micro-operation is generated based on the dependency imposed between the first micro-operation and the second micro-operation. 
     
     
         5 . The method of  claim 2 , wherein the single reservation station entry is generated by encoding the first and the second micro-operations. 
     
     
         6 . The method of  claim 1 , wherein the plurality of results generated by the execution block comprises a first result provided on a first port of the reservation station and a second result provided on a second port of the reservation station. 
     
     
         7 . The method of  claim 6 , wherein the second micro-operation is dispatched after K clock cycles elapses after dispatching the first micro-operation,
 wherein the first micro-operation is completed within K clock cycles,   wherein the second micro-operation is not associated with the plurality of source values,   wherein the second micro-operation establishes the dependency of a second result generated by the execution block using the first micro-operation.   
     
     
         8 . The method of  claim 1 , wherein the instruction represents a 64×64 bit multiplication instruction that generates a 128 bit result, wherein the 128 bit result comprises a lower 64 bit result and a upper 64 bit result, wherein ‘x’ represents a multiplication operation and the plurality of micro-operations comprise the first micro-operation and the second micro-operation. 
     
     
         9 . The method of  claim 8 , wherein the first micro-operation represents a lower 64 bit multiplication operation of the 64×64 bit multiplication instruction and the second micro-operation represents a higher 64 bit multiplication operation of the 64×64 bit multiplication instruction. 
     
     
         10 . The method of  claim 1 , wherein the instruction represents a fused Multiply and Add instruction comprising a third micro-operation and a fourth micro-operation, wherein the third micro-operation is dispatched with a third and a fourth source value and the fourth micro-operation is dispatched to sequence the fifth source value. 
     
     
         11 . The method of  claim 10 , wherein the third micro-operation is dispatched with a third, a fourth and a fifth source value after discarding the fourth micro-operation. 
     
     
         12 . An apparatus comprising:
 an in-order front end unit,   an in-order retire unit, and   an out-of-order execution unit interposed between the in-order front end unit and the in-order retire unit, wherein the out-of-order execution unit further comprises,
 a reservation station is to generate a dependency controlled flow using the plurality of micro-operations, wherein the dependency between a first micro-operation and the second micro-operation of the plurality of micro-operations established by the dependency controlled flow ensures that a second micro-operation is dispatched after a specific delay after dispatching the first micro-operation; and 
 an execution unit coupled to the reservation station, wherein the execution unit is to generate a plurality of results using a plurality of source values received from the reservation station, wherein the plurality of results are provided over a plurality of ports of the reservation station. 
   
     
     
         13 . The apparatus of  claim 12 , wherein the reservation station further comprises a controlled flow generation unit, wherein the controlled flow generation unit is to map a combination of the first micro-operation and the second micro-operation of the plurality of micro-operations into a single reservation station entry, wherein a first set of source values associated with the first micro-operation and a second set of source values associated with the second micro-operation is associated with the single reservation station entry. 
     
     
         14 . The apparatus of  claim 12 , wherein the dependency controlled flow is to assert a line after dispatching a first reservation station entry, wherein the asserted line is to ensure dispatch of the second reservation station entry that is ready, wherein the second reservation station entry is dispatched after a specific delay after the first reservation station entry is dispatched. 
     
     
         15 . The apparatus of  claim 14 , wherein the controlled flow generation unit is to generate the dependency controlled flow comprising the first micro-operation and the second micro-operation based on a dependency imposed between the first and the second micro-operations. 
     
     
         16 . The apparatus of  claim 12 , wherein the controlled flow generation unit is to generate the single reservation station entry by encoding the first micro-operation and the second micro-operation. 
     
     
         17 . The apparatus of  claim 12 , wherein the reservation station further comprises a dispatch unit coupled to the controlled flow generation unit, wherein the dispatch unit is to dispatch the second micro-operation after K clock cycles elapses after dispatching the first micro-operation,
 wherein the first micro-operation is completed within K clock cycles,   wherein the second micro-operation is not associated with the plurality of source values,   wherein the second micro-operation establishes the dependency of a second result generated by the execution block using the first micro-operation.   
     
     
         18 . The apparatus of  claim 12 , wherein the execution unit is to generate the plurality of results comprising a first result of the plurality of results provided on a first port of the plurality of ports of the reservation station and a second result of the plurality of results provided on a second port the plurality of ports of the reservation station. 
     
     
         19 . The apparatus of  claim 18 , wherein the execution unit further comprises:
 a booth encoder, wherein the booth encoder is to receive a first source value,   a first wallace tree multiplier coupled to the booth encoder, wherein the first wallace tree multiplier is to generate an intermediate value in response to receiving the partial products from the booth encoder and the second source value,   a second wallace multiplier coupled to the first wallace multiplier, wherein the second Wallace multiplier is to generate a result using the intermediate value and the second source value,   wherein the execution unit is to provide a first result on a first port of the reservation station and a second result on a second port of the reservation station.   
     
     
         20 . The apparatus of  claim 12 , wherein the controlled flow generation unit is to generate the dependency controlled flow comprising the first and the second micro-operations for a 64×64 bit multiplication instruction that generates a 128 bit result, wherein the 128 bit result comprises a lower 64 bit result and a upper 64 bit result, wherein ‘x’ represents a multiplication operation and the plurality of micro-operations comprise the first and the second micro-operation. 
     
     
         21 . The apparatus  claim 19 , wherein the first micro-operation represents a lower 64 bit multiplication operation of a 64×64 bit multiplication instruction and the second micro-operation represents a higher 64 bit multiplication operation of a 64×64 bit multiplication instruction. 
     
     
         22 . The apparatus of  claim 12 , wherein the controlled flow generation unit is to generate the dependency controlled flow for a fused Multiply and Add instruction comprising a third micro-operation and a fourth micro-operation, wherein the third micro-operation is dispatched with a third and a fourth source value and the fourth micro-operation is dispatched to sequence the fifth source value. 
     
     
         23 . The apparatus of  claim 22 , wherein the third micro-operation is dispatched with a third, a fourth and a fifth source value after discarding the fourth micro-operation.