P

Inventor

HAWKINS ANDREW L

US34 patents
⚠️ This page may combine multiple inventors who share the name “HAWKINS ANDREW L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CYPRESS SEMICONDUCTOR CORP

32 patents
US6005796ADec 21, 1999

Single ended simpler dual port memory cell

CYPRESS SEMICONDUCTOR CORP50 citations96
US5768196AJun 16, 1998

Shift-register based row select circuit with redundancy for a FIFO memory

CYPRESS SEMICONDUCTOR CORP74 citations95
US6731566B1May 4, 2004

Single ended simplex dual port memory cell

CYPRESS SEMICONDUCTOR CORP28 citations92
US6262912B1Jul 17, 2001

Single ended simplex dual port memory cell

CYPRESS SEMICONDUCTOR CORP26 citations92
US5852748ADec 22, 1998

Programmable read-write word line equality signal generation for FIFOs

CYPRESS SEMICONDUCTOR CORP20 citations92
US5828624AOct 27, 1998

Decoder circuit and method for disabling a number of columns or rows in a memory

CYPRESS SEMICONDUCTOR CORP20 citations92
US5712992AJan 27, 1998

State machine design for generating empty and full flags in an asynchronous FIFO

CYPRESS SEMICONDUCTOR CORP21 citations92
US5627797AMay 6, 1997

Full and empty flag generator for synchronous FIFOS

CYPRESS SEMICONDUCTOR CORP21 citations92
US6078637AJun 20, 2000

Address counter test mode for memory device

CYPRESS SEMICONDUCTOR CORP22 citations90
US5850568ADec 15, 1998

Circuit having plurality of carry/sum adders having read count, write count, and offset inputs to generate an output flag in response to FIFO fullness

CYPRESS SEMICONDUCTOR CORP16 citations82
US5862092AJan 19, 1999

Read bitline writer for fallthru in fifos

CYPRESS SEMICONDUCTOR CORP15 citations81
US6181595B1Jan 30, 2001

Single ended dual port memory cell

CYPRESS SEMICONDUCTOR CORP13 citations74
US6070203AMay 30, 2000

Circuit for generating almost full and almost empty flags in response to sum and carry outputs in asynchronous and synchronous FIFOS

CYPRESS SEMICONDUCTOR CORP10 citations74
US5994920ANov 30, 1999

Half-full flag generator for synchronous FIFOs

CYPRESS SEMICONDUCTOR CORP5 citations74
US5963056AOct 5, 1999

Full and empty flag generator for synchronous FIFOs

CYPRESS SEMICONDUCTOR CORP7 citations74
US5955897ASep 21, 1999

Signal generation decoder circuit and method

CYPRESS SEMICONDUCTOR CORP6 citations74
US5809339ASep 15, 1998

State machine design for generating half-full and half-empty flags in an asynchronous FIFO

CYPRESS SEMICONDUCTOR CORP11 citations74
US5661418AAug 26, 1997

Signal generation decoder circuit and method

CYPRESS SEMICONDUCTOR CORP8 citations74
US5936894AAug 10, 1999

Dual level wordline clamp for reduced memory cell current

CYPRESS SEMICONDUCTOR CORP7 citations73
US5860160AJan 12, 1999

High speed FIFO mark and retransmit scheme using latches and precharge

CYPRESS SEMICONDUCTOR CORP7 citations73
US5751644AMay 12, 1998

Data transition detect write control

CYPRESS SEMICONDUCTOR CORP9 citations72
US6813741B1Nov 2, 2004

Address counter test mode for memory device

CYPRESS SEMICONDUCTOR CORP8 citations71
US6510486B1Jan 21, 2003

Clocking scheme for independently reading and writing multiple width words from a memory array

CYPRESS SEMICONDUCTOR CORP5 citations63
US6016403AJan 18, 2000

State machine design for generating empty and full flags in an asynchronous FIFO

CYPRESS SEMICONDUCTOR CORP4 citations63
US5991834ANov 23, 1999

State machine design for generating half-full and half-empty flags in an asynchronous FIFO

CYPRESS SEMICONDUCTOR CORP5 citations63
US5844423ADec 1, 1998

Half-full flag generator for synchronous FIFOs

CYPRESS SEMICONDUCTOR CORP4 citations63
US5880997AMar 9, 1999

Bubbleback for FIFOS

CYPRESS SEMICONDUCTOR CORP5 citations62
US5864507AJan 26, 1999

Dual level wordline clamp for reduced memory cell current

CYPRESS SEMICONDUCTOR CORP4 citations62
US5860118AJan 12, 1999

SRAM write partitioning

CYPRESS SEMICONDUCTOR CORP2 citations62
US5673234ASep 30, 1997

Read bitline writer for fallthru in FIFO's

CYPRESS SEMICONDUCTOR CORP4 citations62
US6023435AFeb 8, 2000

Staggered bitline precharge scheme

CYPRESS SEMICONDUCTOR CORP6 citations61
US6055177AApr 25, 2000

Memory cell

CYPRESS SEMICONDUCTOR CORP2 citations59

CYPRESS SEMICONDUTOR CORP

1 patent

CYPRESS SEMICONDCUTOR CORP

1 patent