Inventor

POTTER TERENCE M

US92 patents

⚠️ This page may combine multiple inventors who share the name “POTTER TERENCE M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

POTTER TERENCE M

INTRINSITY INC

Method and apparatus for TLB memory ordering

Method and apparatus for an enhanced floating point unit with graphics and integer capabilities

Method and apparatus that enforces a regional memory model in hierarchical memory systems

Method and apparatus for a late pipeline enhanced floating point unit

Dynamic adjustment of the clock rate in logic circuits

Method and apparatus for generating clock signals

Method and apparatus for routing 1 of 4 signals

Method and apparatus for routing 1 of N signals

Method and apparatus for logic synchronization

Method and apparatus for a logic circuit with constant power consumption

1-of-4 multiplier

Method and apparatus for N-Nary logic circuit design tool with precharge circuit evaluation

Static storage element for dynamic logic

Method and apparatus for a logic circuit design tool

Method and apparatus for a 1 of N signal

Method and apparatus for logic circuit transition detection

Method and apparatus that supports multiple assignment code

Method and apparatus for logic synchronization

Method and apparatus for an N-NARY logic circuit

Method and apparatus that allows the logic state of a logic gate to be tested when stopping or starting the logic gate&#39;s clock

Method and apparatus for 1 of 4 register file design

Method and apparatus for N-NARY hardware description language

APPLE INC

Providing instruction characteristics to graphics scheduling circuitry based on decoded instructions

Extended multiply

Hardware resource allocation system for allocating resources to threads

SIMD operand permutation with selection from among multiple registers

SIMD operand permutation with selection from among multiple registers

Operand cache control techniques

Operand cache flush, eviction, and clean techniques using hint information and dirty information

Intelligent caching for an operand cache

Operand cache design

Type conversion using floating-point unit

Apparatus implementing instructions that impose pipeline interdependencies

On-demand memory allocation

Instruction-level context switch in SIMD processor

Graphics hardware driven pause for quality of service adjustment

Resource synchronization for graphics processing

Memory allocation techniques for graphics shader

Pipelined allocation for operand cache

Floating-point multiply-add with down-conversion

IBM

Method and system for distributed instruction address translation in a multiscalar data processing system

Combined decoder/adder circuit which provides improved access speed to a cache

Method and system for high speed floating point exception enabled operation in a multiscalar processor system

Method and system in a data processing system for efficient management of an indication of a status of each of multiple registers

EVSX INC

Method and apparatus for logic circuit speed detection

Method and apparatus for a N-nary logic circuit using 1 of N signals

Method and apparatus for a N-nary logic circuit using 1 of 4 signals

POTTER TERENCE M

Result bypass cache

Computer numerical storage format with precision type indicator

MOTOROLA INC

Result normalizer and method of operation

Method and apparatus that allows the logic state of a logic gate to be tested when stopping or starting the logic gate's clock