Inventor

RAMALINGAM SURESH

US65 patents

⚠️ This page may combine multiple inventors who share the name “RAMALINGAM SURESH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RAMALINGAM SURESH

XILINX INC

Multi-die integrated circuits implemented using spacer dies

Integrated electrical/optical interface with two-tiered packaging

Heterogeneous integration module comprising thermal management apparatus

Semiconductor assembly having bridge module for die-to-die interconnection

Substrate-less interposer technology for a stacked silicon interconnect technology (SSIT) product

Methods and apparatus for thermal interface material (TIM) bond line thickness (BLT) reduction and TIM adhesion enhancement for efficient thermal management

Stacked silicon package having a thermal capacitance element

Stacked silicon package assembly having an enhanced lid

Thermal management device with textured surface for extended cooling limit

Warpage management for fan-out mold packaged integrated circuit

Force balanced package mounting

Interposer with edge reinforcement and method for manufacturing same

Integrated circuit package with multi-trench structure on flipped substrate contacting underfill

Solder bump structure with enhanced high temperature aging reliability and method for manufacturing same

Method and apparatus of package enabled ESD protection

Dynamic mounting thermal management for devices on board

Electronic device apparatus with multiple thermally conductive paths for heat dissipation

Micro device with through PCB cooling

Thermal heat spreader plate for electronic device

Package integration for laterally mounted IC dies with dissimilar solder interconnects

Chip package with near-die integrated passive device

Stacked silicon package assembly having vertical thermal management

Remote active cooling heat exchanger and antenna system with the same

Chip package assembly with stress decoupled interconnect layer

Stacked silicon package assembly having thermal management using phase change material

Stacked silicon package assembly having thermal management

Integrated circuit die with in-chip heat sink

Techniques for molded underfill for integrated circuit dies

Chip package assembly with enhanced interconnects and method for fabricating the same

Three-dimensional thermal management apparatuses for electronic devices

Thermal enablement of dies with impurity gettering

Radome with integrated passive cooling

Chip package with pass through heat spreader

Heat spreader for a semiconductor package

Chip package with core embedded integrated devices

Stacked silicon package assembly having thermal management

Modular stacked silicon package assembly

INTEL CORP

Optic switch

Controlled collapse chip connection (C4) integrated circuit package that has a fillet which seals an underfill material

Integrated circuit package having a substrate vent hole

Process for underfilling a controlled collapse chip connection (C4) integrated circuit package with an underfill material that is heated to a partial gel state

Optical subassembly

Controlled collapse chip connection (C4) integrated circuit package which has two dissimilar underfill materials

Process line for underfilling a controlled collapse

High performance via capacitor and method for manufacturing same

JDS UNIPHASE CORP

Redundant package for optical components

Compact, low insertion loss, high yield arrayed waveguide grating

KWON WOON-SEONG

Methods for flip chip stacking

RAMALINGAM SURESH

Process for assembling an integrated circuit package having a substrate vent hole

KIM DONG W

Through-silicon vias with metal system fill