Inventor

IYER SUBRAMANIAN S

US102 patents

⚠️ This page may combine multiple inventors who share the name “IYER SUBRAMANIAN S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IYER SUBRAMANIAN S

IBM

Low defect Si:C layer with retrograde carbon profile

Planar mixed SOI-bulk substrate for microelectronic applications

Method of forming an ultra-uniform silicon-on-insulator layer

Low programming voltage anti-fuse

Substrate for tensilely strained semiconductor

Trench metal-insulator-metal (MIM) capacitors integrated with middle-of-line metal contacts, and method of fabricating same

Double polysilicon process for providing single chip high performance logic and compact embedded memory structure

High speed silicon-based lateral junction photodetectors having recessed electrodes and thick oxide to reduce fringing fields

Modified silicon CMOS process having selectively deposited Si/SiGe FETS

Antifuse structure having an integrated heating element

Trench metal-insulator-metal (MIM) capacitors and method of fabricating same

Low-cost deep trench decoupling capacitor device and process of manufacture

Secure and dense SRAM cells in EDRAM technology

Silicon-based rib waveguide optical modulator

Gate electrode sidewall isolation spacer for field effect transistors

Method for differential selective deposition of metal for fabricating metal contacts in integrated semiconductor circuits

Self-authenticating of chip based on intrinsic features

Embedded charge trap multi-time-programmable-read-only-memory for high performance logic technology

Programmable fuse/non-volatile memory structures using externally heated phase change material

Gain cell structure with deep trench capacitor

Semiconductor chip having both compact memory and high performance logic

Method for reducing surface oxide in polysilicon processing

Immersion scanning system for fabricating porous silicon films

Formation of 3-dimensional silicon silicide structures

Method of forming uniformly thin, isolated silicon mesas on an insulating substrate

DRAM cell buried strap leakage measurement structure and method

Providing an authenticating service of a chip

Array of processor core circuits with reversible tiers

Non-volatile memory based on retention modulation

Front side wafer ID processing

3D integration structure and method using bonded metal planes

Four-terminal antifuse structure having integrated heating elements for a programmable circuit

Trench metal-insulator metal (MIM) capacitors

Electrical fuse structure for higher post-programming resistance

Dense semiconductor fuse array

High on-current device for high performance embedded DRAM (eDRAM) and method of forming the same

Wiring structure for trench fuse component with methods of fabrication

FAROOQ MUKTA G

Method of making 3D integrated circuits

3D integrated circuit device fabrication with precisely controllable substrate removal

Three dimensional integrated circuit integration using dielectric bonding first and through via formation last

3D integrated circuits structure

3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer

3D integrated circuit device fabrication using interface wafer as permanent carrier

MOTOROLA INC

Network for a cellular communication system and a method of operation therefor

SIBOND L L C

Single-etch stop process for the manufacture of silicon-on-insulator wafers

GLOBALFOUNDRIES INC

Method to achieve ultra-high chip-to-chip alignment accuracy for wafer-to-wafer bonding process

(unassigned)

Layered structure of a substrate, a dielectric layer and a single crystal layer

SI BOND LLC

Single-etch stop process for the manufacture of silicon-on-insulator substrates

GLOBALFOUNDRIES US 2 LLC

Physically unclonable fuse using a NOR type memory array

ANDRY PAUL S

Optimized annular copper TSV