Inventor

JEONG BYUNG HOON

KR55 patents

⚠️ This page may combine multiple inventors who share the name “JEONG BYUNG HOON”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JEONG BYUNG HOON

SAMSUNG ELECTRONICS CO LTD

Nonvolatile memory including on-die-termination circuit and storage device including the nonvolatile memory

Nonvolatile memory including on-die-termination circuit and storage device including the nonvolatile memory

Buffer device supporting training operations for a plurality of memory devices, and memory module and memory system each including the buffer device

Nonvolatile memory including on-die-termination circuit and storage device including the nonvolatile memory

Nonvolatile memory including on-die-termination circuit and storage device including the nonvolatile memory

Nonvolatile memory including on-die-termination circuit and storage device including the nonvolatile memory

Semiconductor memory device correcting fuse data and method of operating the same

Circuit and method for controlling inversion of delay locked loop and delay locked loop and synchronous semiconductor memory device using the same

Nonvolatile memory including duty correction circuit and storage device including the nonvolatile memory

Reception interface circuits supporting multiple communication standards and memory systems including the same

Method and circuit for self-training of a reference voltage and memory system including the same

Latency circuit using division method related to CAS latency and semiconductor memory device

CAS latency circuit and semiconductor memory device including the same

Repair circuit and method of repairing defects in a semiconductor memory device

Internal signal replication device and method

Nonvolatile memory including on-die-termination circuit and storage device including the nonvolatile memory

Time delay compensation circuit comprising delay cells having various unit time delays

Storage system for enhancing data valid windows of signals

Defect detection structure of a semiconductor die, semiconductor device including the same and method of detecting defects in semiconductor die

Defect detection structure of a semiconductor die, semiconductor device including the same and method of detecting defects in semiconductor die

Nonvolatile memory including duty correction circuit and storage device including the nonvolatile memory

Non-volatile memory device

Shared decoupling capacitance

Non-volatile memory device and storage device including the same

Memory device for efficiently determining whether to perform re-training operation and memory system including the same

Non-volatile memory device and storage device including the same

Non-volatile memory device and storage device including the same

Latency control circuit and method using queuing design method

Memory device including on-die-termination circuit

Storage system for enhancing data valid windows of signals

Nonvolatile memory including on-die-termination circuit and storage device including the nonvolatile memory

Non-volatile memory device

Memory device including on-die-termination circuit

Nonvolatile memory device, memory system including the same and method of operating the same

Nonvolatile memory including duty correction circuit and storage device including the nonvolatile memory

Non-volatile memory device

Memory device including on-die-termination circuit

Method and circuit for self-training of a reference voltage and memory system including the same

Memory devices and memory systems including the same

Synchronous semiconductor device having constant data output time regardless of bit organization, and method of adjusting data output time

Memory device for efficiently determining whether to perform re-training operation and memory system including the same

Memory device for efficiently determining whether to perform re-training operation and memory system including the same

Nonvolatile memory device

Memory device including on-die-termination circuit

Semiconductor memory device correcting fuse data and method of operating the same

Delay-locked loop, integrated circuit having the same, and method of driving the same

Reference voltage generator and semiconductor device including the same

KANG DAE WOON

Nonvolatile memory device, memory system including the same and method of operating the same

KWON SANG-HYUK

Clock signal generation circuit for reducuing current consumption, and semiconductor device having the same

JEONG BYUNG-HOON

Latency control circuit and method using queuing design method