Inventor · disambiguated record
Chandra Gurram
Also filed as: GURRAM CHANDRA · GURRAM CHANDRA S
35 granted patents·11 pending applications·120 citations·filing 2016–2025
96Inventor score
Files withINTEL CORP46
Top patents by PatentIndex Score
46 records- 0198US12007935B2Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point formatINTEL CORP·Filed 2020·Granted Jun 11, 2024·11 cites·25 claims
- 0298US11709793B2Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point formatINTEL CORP·Filed 2022·Granted Jul 25, 2023·9 cites·16 claims
- 0398US11361496B2Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point formatINTEL CORP·Filed 2021·Granted Jun 14, 2022·41 cites·23 claims
- 0497US11954063B2Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point formatINTEL CORP·Filed 2023·Granted Apr 9, 2024·2 cites·23 claims
- 0597US11182337B1Computing efficient cross channel operations in parallel computing machines using systolic arraysINTEL CORP·Filed 2020·Granted Nov 23, 2021·9 cites·20 claims
- 0696US11204977B2Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputsINTEL CORP·Filed 2020·Granted Dec 21, 2021·7 cites·20 claims
- 0794US11636174B2Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputsINTEL CORP·Filed 2021·Granted Apr 25, 2023·3 cites·20 claims
- 0893US10983581B2Resource load balancing based on usage and power limitsINTEL CORP·Filed 2017·Granted Apr 20, 2021·12 cites·27 claims
- 0993US10360654B1Software scoreboard information and synchronizationINTEL CORP·Filed 2018·Granted Jul 23, 2019·16 cites·20 claims
- 1090US2024362180A1Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point formatINTEL CORP·Filed 2024·Application pending·0 cites
- 1189US11977885B2Utilizing structured sparsity in systolic arraysINTEL CORP·Filed 2020·Granted May 7, 2024·2 cites·20 claims
- 1285US11669490B2Computing efficient cross channel operations in parallel computing machines using systolic arraysINTEL CORP·Filed 2021·Granted Jun 6, 2023·1 cites·20 claims
- 1384US11042370B2Instruction and logic for systolic dot product with accumulateINTEL CORP·Filed 2018·Granted Jun 22, 2021·3 cites·20 claims
- 1483US12346694B2Register file for systolic arrayINTEL CORP·Filed 2021·Granted Jul 1, 2025·1 cites·20 claims
- 1582US12189571B2Dual pipeline parallel systolic arrayINTEL CORP·Filed 2021·Granted Jan 7, 2025·1 cites·20 claims
- 1680US12405787B2Utilizing structured sparsity in systolic arraysINTEL CORP·Filed 2024·Granted Sep 2, 2025·0 cites·20 claims
- 1780US2025199863A1Using sparsity metadata to reduce systolic array power consumptionINTEL CORP·Filed 2024·Application pending·0 cites
- 1879US2024427847A1Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputsINTEL CORP·Filed 2024·Application pending·0 cites
- 1977US12039001B2Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputsINTEL CORP·Filed 2023·Granted Jul 16, 2024·0 cites·20 claims
- 2077US2025390307A1Register file for systolic arrayINTEL CORP·Filed 2025·Application pending·0 cites
- 2175US12093213B2Computing efficient cross channel operations in parallel computing machines using systolic arraysINTEL CORP·Filed 2023·Granted Sep 17, 2024·0 cites·20 claims
- 2275US2025117360A1Systolic array of arbitrary physical and logical depthINTEL CORP·Filed 2024·Application pending·0 cites
- 2373US11163578B2Systems and methods for reducing register bank conflicts based on a software hint bit causing a hardware thread switchINTEL CORP·Filed 2018·Granted Nov 2, 2021·1 cites·12 claims
- 2473US2025117359A1Dual pipeline parallel systolic arrayINTEL CORP·Filed 2024·Application pending·0 cites
- 2573US2025199858A1Multiple register allocation sizes for threadsINTEL CORP·Filed 2024·Application pending·0 cites
- 2672US2023297373A1Instruction and logic for systolic dot product with accumulateINTEL CORP·Filed 2023·Application pending·0 cites
- 2771US11900502B2Compiler assisted register file write reductionINTEL CORP·Filed 2022·Granted Feb 13, 2024·0 cites·20 claims
- 2871US10983794B2Register sharing mechanismINTEL CORP·Filed 2019·Granted Apr 20, 2021·1 cites·21 claims
- 2969US11640297B2Instruction and logic for systolic dot product with accumulateINTEL CORP·Filed 2021·Granted May 2, 2023·0 cites·20 claims
- 3067US12190158B2Using sparsity metadata to reduce systolic array power consumptionINTEL CORP·Filed 2021·Granted Jan 7, 2025·0 cites·20 claims
- 3167US12174783B2Systolic array of arbitrary physical and logical depthINTEL CORP·Filed 2021·Granted Dec 24, 2024·0 cites·20 claims
- 3266US12386617B2Gathering payload from arbitrary registers for send messages in a graphics environmentINTEL CORP·Filed 2021·Granted Aug 12, 2025·0 cites·20 claims
- 3366US11669329B2Instructions and logic for vector multiply add with zero skippingINTEL CORP·Filed 2022·Granted Jun 6, 2023·0 cites·20 claims
- 3464US12399685B2Systolic array having support for output sparsityINTEL CORP·Filed 2021·Granted Aug 26, 2025·0 cites·20 claims
- 3564US12210905B2Multiple register allocation sizes for threadsINTEL CORP·Filed 2021·Granted Jan 28, 2025·0 cites·20 claims
- 3663US2022179655A1Systems and methods for reducing register bank conflicts based on software hint and hardware thread switchINTEL CORP·Filed 2021·Application pending·0 cites
- 3762US11321799B2Compiler assisted register file write reductionINTEL CORP·Filed 2019·Granted May 3, 2022·0 cites·26 claims
- 3862US11314515B2Instructions and logic for vector multiply add with zero skippingINTEL CORP·Filed 2019·Granted Apr 26, 2022·0 cites·20 claims
- 3959US10692170B2Software scoreboard information and synchronizationINTEL CORP·Filed 2019·Granted Jun 23, 2020·0 cites·20 claims
- 4058US10769751B2Single input multiple data processing mechanismINTEL CORP·Filed 2019·Granted Sep 8, 2020·0 cites·6 claims
- 4154US12333306B2High performance constant cache and constant access mechanismsINTEL CORP·Filed 2021·Granted Jun 17, 2025·0 cites·14 claims
- 4254US10839478B2Accumulator pooling mechanismINTEL CORP·Filed 2019·Granted Nov 17, 2020·0 cites·22 claims
- 4352US10417730B2Single input multiple data processing mechanismINTEL CORP·Filed 2016·Granted Sep 17, 2019·0 cites·9 claims
- 4444US10754651B2Register bank conflict reduction for multi-threaded processorINTEL CORP·Filed 2018·Granted Aug 25, 2020·0 cites·16 claims
- 4544US2021349717A1Compaction of diverged lanes for efficient use of alusINTEL CORP·Filed 2020·Application pending·0 cites
- 4640US2019265973A1Fusion of SIMD Processing UnitsINTEL CORP·Filed 2018·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →