Fusion of SIMD Processing Units

Abstract

Methods and apparatus relating to techniques for fusing SIMD processing units. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive an instruction set for execution on at least two graphics processing execution units, determine whether the instruction set requires data dependent addressing, and select between a synchronized execution environment for the at least two graphics processing units and an unsynchronized execution environment for the at least two graphics processing units based at least in part on the determination whether the instruction set requires data dependent addressing. Other embodiments are also disclosed and claimed.

1 . An apparatus comprising:
 logic, at least partially comprising hardware logic, to:
 receive an instruction set for execution on at least two graphics processing execution units; 
 determine whether the instruction set requires data dependent addressing; and 
 select between a synchronized execution environment for the at least two graphics processing units and an unsynchronized execution environment for the at least two graphics processing units based at least in part on the determination whether the instruction set requires data dependent addressing. 
   
     
     
         2 . The apparatus of  claim 1 , further comprising logic, at least partially including hardware logic, to:
 determine that the instruction set does not require data dependent addressing, and in response to the determination, to:   synchronize transmission of the instructions on a data bus coupled to the at least two execution units.   
     
     
         3 . The apparatus of  claim 2 , further comprising logic, at least partially including hardware logic, to:
 synchronize execution of the instructions on the at least two execution units.   
     
     
         4 . The apparatus of  claim 1 , further comprising logic, at least partially including hardware logic, to:
 determine that the instruction set requires data dependent addressing, and in response to the determination, to:   sequence transmission of the instructions on a data bus coupled to the at least two execution units serially.   
     
     
         5 . The apparatus of  claim 4 , further comprising logic, at least partially including hardware logic, to:
 execute the instructions on the at least two execution units serially.   
     
     
         6 . An electronic device, comprising:
 a processor having one or more processor cores;   logic, at least partially comprising hardware logic, to:
 receive an instruction set for execution on at least two graphics processing execution units; 
 determine whether the instruction set requires data dependent addressing; and 
 select between a synchronized execution environment for the at least two graphics processing units and an unsynchronized execution environment for the at least two graphics processing units based at least in part on the determination whether the instruction set requires data dependent addressing. 
   
     
     
         7 . The electronic device of  claim 6  further comprising logic, at least partially including hardware logic, to:
 determine that the instruction set does not require data dependent addressing, and in response to the determination, to: 
 synchronize transmission of the instructions on a data bus coupled to the at least two execution units. 
 
     
     
         8 . The electronic device of  claim 7 , further comprising logic, at least partially including hardware logic, to:
 synchronize execution of the instructions on the at least two execution units.   
     
     
         9 . The electronic device of  claim 6 , further comprising logic, at least partially including hardware logic, to:
 determine that the instruction set requires data dependent addressing, and in response to the determination, to:   sequence transmission of the instructions on a data bus coupled to the at least two execution units serially.   
     
     
         10 . The electronic device of  claim 9 , further comprising logic, at least partially including hardware logic, to:
 further comprising logic, at least partially including hardware logic, to:
 execute the instructions on the at least two execution units serially 
   
     
     
         11 . A method comprising:
 receive an instruction set for execution on at least two graphics processing execution units;   determine whether the instruction set requires data dependent addressing; and   select between a synchronized execution environment for the at least two graphics processing units and an unsynchronized execution environment for the at least two graphics processing units based at least in part on the determination whether the instruction set requires data dependent addressing.   
     
     
         12 . The method of  claim 11 , further comprising:
 determine that the instruction set does not require data dependent addressing, and in response to the determination, to:   synchronize transmission of the instructions on a data bus coupled to the at least two execution units.   
     
     
         13 . The method of  claim 12 , further comprising:
 synchronize execution of the instructions on the at least two execution units.   
     
     
         14 . The method of  claim 11 , further comprising logic, at least partially including hardware logic, to:
 determine that the instruction set requires data dependent addressing, and in response to the determination, to:   sequence transmission of the instructions on a data bus coupled to the at least two execution units serially.   
     
     
         15 . The method of  claim 14 , further comprising logic, at least partially including hardware logic, to:
 execute the instructions on the at least two execution units serially.   
     
     
         16 . One or more computer-readable medium comprising one or more instructions that when executed on at least one processor configure the at least one processor to perform one or more operations to:
 receive an instruction set for execution on at least two graphics processing execution units;   determine whether the instruction set requires data dependent addressing; and   select between a synchronized execution environment for the at least two graphics processing units and an unsynchronized execution environment for the at least two graphics processing units based at least in part on the determination whether the instruction set requires data dependent addressing.   
     
     
         17 . The computer-readable medium of  claim 16 , comprising one or more instructions that when executed on the at least one processor configure the at least one processor to:
 determine that the instruction set does not require data dependent addressing, and in response to the determination, to:   synchronize transmission of the instructions on a data bus coupled to the at least two execution units.   
     
     
         18 . The computer-readable medium of  claim 17 , further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to:
 synchronize execution of the instructions on the at least two execution units.   
     
     
         19 . The computer-readable medium of  claim 16 , further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to:
 determine that the instruction set requires data dependent addressing, and in response to the determination, to:   sequence transmission of the instructions on a data bus coupled to the at least two execution units serially.   
     
     
         20 . The computer-readable medium of  claim 19 , further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to:
 execute the instructions on the at least two execution units serially