Inventor · disambiguated record
Rahul K. Nadkarni
Also filed as: NADKARNI RAHUL · NADKARNI RAHUL K · NADKARNI RAHUL KRISHNAKUMAR
19 granted patents·3 pending applications·136 citations·filing 2001–2022
94Inventor score
Top patents by PatentIndex Score
22 records- 0191US8233302B2Content addressable memory with concurrent read and search/compare operations at the same memory cellARSOVSKI IGOR·Filed 2011·Granted Jul 31, 2012·14 cites·9 claims
- 0291US7924588B2Content addressable memory with concurrent two-dimensional search capability in both row and column directionsIBM·Filed 2007·Granted Apr 12, 2011·23 cites·21 claims
- 0380US7515449B2CAM asynchronous search-line switchingIBM·Filed 2006·Granted Apr 7, 2009·10 cites·16 claims
- 0476US9768779B2Voltage level shifters employing preconditioning circuits, and related systems and methodsQUALCOMM INC·Filed 2015·Granted Sep 19, 2017·3 cites·27 claims
- 0575US9557378B2Method and structure for multi-core chip product test and selective voltage binning dispositionBICKFORD JEANNE P·Filed 2012·Granted Jan 31, 2017·3 cites·25 claims
- 0671US9396794B1Matchline retention for mitigating search and write conflictQUALCOMM INC·Filed 2015·Granted Jul 19, 2016·3 cites·21 claims
- 0770US6920525B2Method and apparatus of local word-line redundancy in CAMIBM·Filed 2002·Granted Jul 19, 2005·18 cites·11 claims
- 0870US6597596B2Content addressable memory having cascaded sub-entry architectureIBM·Filed 2002·Granted Jul 22, 2003·16 cites·21 claims
- 0966US6512684B2Content addressable memory having cascaded sub-entry architectureIBM·Filed 2001·Granted Jan 28, 2003·14 cites·13 claims
- 1066US6430072B1Embedded CAM test structure for fully testing all matchlinesIBM·Filed 2001·Granted Aug 6, 2002·15 cites·17 claims
- 1163US11223359B2Power efficient voltage level translator circuitQUALCOMM INC·Filed 2016·Granted Jan 11, 2022·1 cites·24 claims
- 1260US12056052B2Data L2 cache with split accessAMPERE COMPUTING LLC·Filed 2022·Granted Aug 6, 2024·0 cites·20 claims
- 1360US7619923B2Apparatus for reducing leakage in global bit-line architecturesIBM·Filed 2007·Granted Nov 17, 2009·4 cites·5 claims
- 1453US6552920B2Saving content addressable memory power through conditional comparisonsIBM·Filed 2001·Granted Apr 22, 2003·7 cites·24 claims
- 1544US12087383B2Virtualized scan chain testing in a random access memory (RAM) arrayAMPERE COMPUTING LLC·Filed 2022·Granted Sep 10, 2024·0 cites·22 claims
- 1644US8873269B2Read only memory bitline load-balancingIBM·Filed 2013·Granted Oct 28, 2014·1 cites·26 claims
- 1741US6711040B2Saving content addressable memory power through conditional comparisonsIBM·Filed 2003·Granted Mar 23, 2004·4 cites·15 claims
- 1838US10559352B2Bitline-driven sense amplifier clocking schemeQUALCOMM INC·Filed 2018·Granted Feb 11, 2020·0 cites·28 claims
- 1937US9666269B2Collision detection systems for detecting read-write collisions in memory systems after word line activation, and related systems and methodsQUALCOMM INC·Filed 2015·Granted May 30, 2017·0 cites·19 claims
- 2037US2009141530A1Structure for implementing enhanced content addressable memory performance capabilityIBM·Filed 2008·Application pending·0 cites
- 2134US2018152176A1Voltage aware circuit for dual voltage domain signalsQUALCOMM INC·Filed 2016·Application pending·0 cites
- 2234US2008046789A1Apparatus and method for testing memory devices and circuits in integrated circuitsARSOVSKI IGOR·Filed 2006·Application pending·0 cites
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