Inventor · disambiguated record
Robert D. Herzl
Also filed as: HERZL ROBERT D · HERZL ROBERT DOV
31 granted patents·3 pending applications·465 citations·filing 1988–2018
97Inventor score
Top patents by PatentIndex Score
34 records- 0194US6539522B1Method of developing re-usable software for efficient verification of system-on-chip integrated circuit designsIBM·Filed 2000·Granted Mar 25, 2003·90 cites·32 claims
- 0292US6615167B1Processor-independent system-on-chip verification for embedded processor systemsIBM·Filed 2000·Granted Sep 2, 2003·100 cites·19 claims
- 0387US9097765B1Performance screen ring oscillator formed from multi-dimensional pairings of scan chainsIBM·Filed 2014·Granted Aug 4, 2015·10 cites·20 claims
- 0486US9128151B1Performance screen ring oscillator formed from paired scan chainsIBM·Filed 2014·Granted Sep 8, 2015·6 cites·20 claims
- 0585US9383766B2Chip performance monitoring system and methodIBM·Filed 2013·Granted Jul 5, 2016·5 cites·20 claims
- 0685US7480888B1Design structure for facilitating engineering changes in integrated circuitsIBM·Filed 2008·Granted Jan 20, 2009·14 cites·3 claims
- 0780US8464199B1Circuit design using design variable function slope sensitivityCHARLEBOIS MARGARET R·Filed 2012·Granted Jun 11, 2013·7 cites·12 claims
- 0880US6487699B1Method of controlling external models in system-on-chip verificationIBM·Filed 2000·Granted Nov 26, 2002·28 cites·41 claims
- 0979US9188643B2Flexible performance screen ring oscillator within a scan chainIBM·Filed 2012·Granted Nov 17, 2015·4 cites·20 claims
- 1078US10006964B2Chip performance monitoring system and methodIBM·Filed 2016·Granted Jun 26, 2018·2 cites·20 claims
- 1168US8060845B2Minimizing impact of design changes for integrated circuit designsHERZL ROBERT D·Filed 2008·Granted Nov 15, 2011·4 cites·6 claims
- 1267US8141028B2Structure for identifying and implementing flexible logic block logic for easy engineering changesHERZL ROBERT D·Filed 2008·Granted Mar 20, 2012·4 cites·2 claims
- 1367US6868545B1Method for re-using system-on-chip verification software in an operating systemIBM·Filed 2000·Granted Mar 15, 2005·14 cites·24 claims
- 1467US5032985AMultiprocessor system with memory fetch buffer invoked during cross-interrogationIBM·Filed 1988·Granted Jul 16, 1991·45 cites·15 claims
- 1566US10599569B2Maintaining consistency between address translations in a data processing systemIBM·Filed 2016·Granted Mar 24, 2020·1 cites·17 claims
- 1661US8754696B2Ring oscillatorCHARLEBOIS MARGARET R·Filed 2012·Granted Jun 17, 2014·2 cites·16 claims
- 1761US8667223B2Shadow registers for least recently used data in cacheCHADWICK JR THOMAS B·Filed 2011·Granted Mar 4, 2014·2 cites·12 claims
- 1860US7917348B2Method of switching external models in an automated system-on-chip integrated circuit design verification systemIBM·Filed 2008·Granted Mar 29, 2011·1 cites·13 claims
- 1960US7353156B2Method of switching external models in an automated system-on-chip integrated circuit design verification systemIBM·Filed 2002·Granted Apr 1, 2008·6 cites·10 claims
- 2059US8341588B2Semiconductor layer forming method and structureHERZL ROBERT D·Filed 2010·Granted Dec 25, 2012·1 cites·19 claims
- 2159US5930832AApparatus to guarantee TLB inclusion for store operationsIBM·Filed 1996·Granted Jul 27, 1999·37 cites·6 claims
- 2258US8181148B2Method for identifying and implementing flexible logic block logic for easy engineering changesHERZL ROBERT D·Filed 2008·Granted May 15, 2012·1 cites·17 claims
- 2355US10884943B2Speculative checkin of ERAT cache entriesIBM·Filed 2018·Granted Jan 5, 2021·0 cites·20 claims
- 2449US5269009AProcessor system with improved memory transfer meansIBM·Filed 1990·Granted Dec 7, 1993·25 cites·4 claims
- 2548US6157981AReal time invariant behavior cacheIBM·Filed 1998·Granted Dec 5, 2000·22 cites·11 claims
- 2648US2012167022A1Method and device for identifying and implementing flexible logic block logic for easy engineering changesHERZL ROBERT D·Filed 2012·Application pending·0 cites
- 2747US9286129B2Termination of requests in a distributed coprocessor systemIBM·Filed 2013·Granted Mar 15, 2016·0 cites·13 claims
- 2846US11221957B2Promotion of ERAT cache entriesIBM·Filed 2018·Granted Jan 11, 2022·0 cites·18 claims
- 2946US2009045839A1Asic logic library of flexible logic blocks and method to enable engineering changeIBM·Filed 2007·Application pending·0 cites
- 3045US2009045836A1Asic logic library of flexible logic blocks and method to enable engineering changeHERZL ROBERT D·Filed 2007·Application pending·0 cites
- 3143US5835714AMethod and apparatus for reservation of data buses between multiple storage control elementsIBM·Filed 1995·Granted Nov 10, 1998·14 cites·3 claims
- 3242US5953510ABidirectional data bus reservation priority controls having token logicIBM·Filed 1991·Granted Sep 14, 1999·11 cites·6 claims
- 3339US10169500B2Critical path delay predictionCHARLEBOIS MARGARET R·Filed 2011·Granted Jan 1, 2019·0 cites·17 claims
- 3434US5361368ACross interrogate synchronization mechanism including logic means and delay registerIBM·Filed 1991·Granted Nov 1, 1994·9 cites·6 claims
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