Method and device for identifying and implementing flexible logic block logic for easy engineering changes

Abstract

A chip design methodology and an integrated circuit chip. The methodology includes identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB).

1 . A chip design methodology comprising:
 identifying engineering changeable logic; and   replacing the identified engineering changeable logic with flexible logic blocks (FLB).   
     
     
         2 . The chip design methodology in accordance with  claim 1 , wherein the identifying engineering changeable logic includes tagging logic related to at least one of: new or asynchronous interfaces; new functions; an inexperienced designer; late date design changes; low verification coverage; and bug fixes made to the logic. 
     
     
         3 . The chip design methodology in accordance with  claim 2 , further comprising:
 prioritizing the tagged logic; and   replacing the tagged logic with flexible logic blocks according to the prioritizing.   
     
     
         4 . The chip design methodology in accordance with  claim 1 , wherein the identified engineering changeable logic is replaced with flexible logic blocks using synthesis directives or synthesis script of a synthesis tool. 
     
     
         5 . The chip design methodology in accordance with  claim 1 , wherein the identified engineering changeable logic is replaced with flexible logic blocks using an FLB library of a post-processing tool. 
     
     
         6 . The chip design methodology in accordance with  claim 1 , further comprising:
 saving a netlist of design logic; and   comparing the saved netlist to a subsequent netlist,   wherein at least one of a new function, a non-equivalent function, a new design, or part of a fix is identified as engineering changeable logic to be replaced with flexible logic blocks.   
     
     
         7 . The chip design methodology in accordance with  claim 1 , further comprising:
 copying the identified engineering changeable logic to obtain original identified engineering changeable logic and copy identified engineering changeable logic, wherein the identified engineering changeable logic replaced with flexible logic blocks comprises the copy identified engineering changeable logic; and   selecting at least one of the original identified engineering changeable logic and the copy identified changeable logic replaced with flexible logic blocks.   
     
     
         8 . The chip design methodology in accordance with  claim 7 , wherein, when more flexibility is desired, the method further comprises converting at least some of the original engineering changeable logic to flexible logic blocks. 
     
     
         9 . An integrated circuit chip, comprising:
 a device for identifying engineering changeable logic; and   a replacing device for replacing the identified engineering changeable logic with flexible logic blocks (FLB).   
     
     
         10 . The integrated circuit chip in accordance with  claim 9 , wherein the replacing device comprises a synthesizing tool. 
     
     
         11 . The integrated circuit chip in accordance with  claim 9 , wherein the replacement device comprises a post-processing tool. 
     
     
         12 . The integrated circuit chip in accordance with  claim 9 , wherein the device for identifying engineering changeable logic comprises a device to tag logic related to at least one of: new or asynchronous interfaces; new functions; inexperienced designer; late date design changes; low verification coverage; and bug fixes made to the logic. 
     
     
         13 . The integrated circuit chip in accordance with  claim 9 , wherein the identified engineering changeable logic comprise cones of logic having a plurality of outputs of which at least one of outputs requires a change. 
     
     
         14 . The integrated circuit chip in accordance with  claim 9 , further comprising:
 a first netlist of design logic;   a subsequent netlist; and   a comparison unit for comparing the first netlist to the subsequent netlist,   wherein at least one of a new function, a non-equivalent function, a new design, or part of a fix is identified as engineering changeable logic to be replaced with flexible logic blocks.   
     
     
         15 . The integrated circuit chip in accordance with  claim 14 , wherein the comparison unit comprises a logical equivalency testing tool. 
     
     
         16 . The integrated circuit chip in accordance with  claim 9 , wherein the device for identifying engineering changeable logic comprises a device to tag logic related to new or asynchronous interfaces. 
     
     
         17 . The integrated circuit chip in accordance with  claim 9 , wherein the device for identifying engineering changeable logic comprises a device to tag logic related to new functions. 
     
     
         18 . The integrated circuit chip in accordance with  claim 9 , wherein the device for identifying engineering changeable logic comprises a device to tag logic related to late date design changes. 
     
     
         19 . The integrated circuit chip in accordance with  claim 9 , wherein the device for identifying engineering changeable logic comprises a device to tag logic related to low verification coverage. 
     
     
         20 . The integrated circuit chip in accordance with  claim 9 , wherein the device for identifying engineering changeable logic comprises a device to tag logic related to bug fixes made to the logic.