Inventor · disambiguated record
David W. Milton
Also filed as: MILTON DAVID W · MILTON DAVID WILLS
45 granted patents·9 pending applications·562 citations·filing 1987–2016
98Inventor score
Top patents by PatentIndex Score
54 records- 0194US6539522B1Method of developing re-usable software for efficient verification of system-on-chip integrated circuit designsIBM·Filed 2000·Granted Mar 25, 2003·90 cites·32 claims
- 0290US7240266B2Clock control circuit for test that facilitates an at speed structural testIBM·Filed 2005·Granted Jul 3, 2007·23 cites·37 claims
- 0390US5046844AApparatus for inspecting and hangering shirtsCINTAS CORP·Filed 1988·Granted Sep 10, 1991·47 cites·13 claims
- 0489US6427224B1Method for efficient verification of system-on-chip integrated circuit designs including an embedded processorIBM·Filed 2000·Granted Jul 30, 2002·67 cites·26 claims
- 0589US4873878AApparatus for inspecting and hangering pantsCINTAS CORP·Filed 1987·Granted Oct 17, 1989·37 cites·24 claims
- 0687US9097765B1Performance screen ring oscillator formed from multi-dimensional pairings of scan chainsIBM·Filed 2014·Granted Aug 4, 2015·10 cites·20 claims
- 0786US9128151B1Performance screen ring oscillator formed from paired scan chainsIBM·Filed 2014·Granted Sep 8, 2015·6 cites·20 claims
- 0885US9383766B2Chip performance monitoring system and methodIBM·Filed 2013·Granted Jul 5, 2016·5 cites·20 claims
- 0985US7480888B1Design structure for facilitating engineering changes in integrated circuitsIBM·Filed 2008·Granted Jan 20, 2009·14 cites·3 claims
- 1084US7849362B2Method and system of coherent design verification of inter-cluster interactionsIBM·Filed 2005·Granted Dec 7, 2010·14 cites·19 claims
- 1182US7996807B2Integrated test waveform generator (TWG) and customer waveform generator (CWG), design structure and methodIBM·Filed 2008·Granted Aug 9, 2011·11 cites·20 claims
- 1280US8464199B1Circuit design using design variable function slope sensitivityCHARLEBOIS MARGARET R·Filed 2012·Granted Jun 11, 2013·7 cites·12 claims
- 1380US6507230B1Clock generator having a deskewerIBM·Filed 2000·Granted Jan 14, 2003·29 cites·11 claims
- 1480US6487699B1Method of controlling external models in system-on-chip verificationIBM·Filed 2000·Granted Nov 26, 2002·28 cites·41 claims
- 1579US9188643B2Flexible performance screen ring oscillator within a scan chainIBM·Filed 2012·Granted Nov 17, 2015·4 cites·20 claims
- 1678US10006964B2Chip performance monitoring system and methodIBM·Filed 2016·Granted Jun 26, 2018·2 cites·20 claims
- 1777US7768325B2Circuit and design structure for synchronizing multiple digital signalsIBM·Filed 2008·Granted Aug 3, 2010·8 cites·10 claims
- 1875US7451070B2Optimal bus operation performance in a logic simulation environmentIBM·Filed 2005·Granted Nov 11, 2008·6 cites·3 claims
- 1975US6865502B2Method and system for logic verification using mirror interfaceIBM·Filed 2001·Granted Mar 8, 2005·17 cites·5 claims
- 2073US5727180AMemory including master and local word lines coupled to memory cells storing access informationIBM·Filed 1995·Granted Mar 10, 1998·28 cites·7 claims
- 2169US8189723B2Method, circuit, and design structure for capturing data across a pseudo-synchronous interfaceBERHANU MALEDE W·Filed 2008·Granted May 29, 2012·8 cites·15 claims
- 2268US8060845B2Minimizing impact of design changes for integrated circuit designsHERZL ROBERT D·Filed 2008·Granted Nov 15, 2011·4 cites·6 claims
- 2368US7711534B2Method and system of design verificationIBM·Filed 2005·Granted May 4, 2010·4 cites·22 claims
- 2467US8141028B2Structure for identifying and implementing flexible logic block logic for easy engineering changesHERZL ROBERT D·Filed 2008·Granted Mar 20, 2012·4 cites·2 claims
- 2566US7529962B1System for expanding a window of valid dataIBM·Filed 2008·Granted May 5, 2009·3 cites·1 claims
- 2664US6075415ADigital frequency multiplierIBM·Filed 1999·Granted Jun 13, 2000·27 cites·23 claims
- 2762US7515666B2Method for dynamically changing the frequency of clock signalsIBM·Filed 2005·Granted Apr 7, 2009·2 cites·3 claims
- 2861US8754696B2Ring oscillatorCHARLEBOIS MARGARET R·Filed 2012·Granted Jun 17, 2014·2 cites·16 claims
- 2961US7353131B2Method and system for logic verification using mirror interfaceIBM·Filed 2004·Granted Apr 1, 2008·6 cites·2 claims
- 3060US8736340B2Differential clock signal generatorMILTON DAVID W·Filed 2012·Granted May 27, 2014·2 cites·14 claims
- 3160US7917348B2Method of switching external models in an automated system-on-chip integrated circuit design verification systemIBM·Filed 2008·Granted Mar 29, 2011·1 cites·13 claims
- 3260US7353156B2Method of switching external models in an automated system-on-chip integrated circuit design verification systemIBM·Filed 2002·Granted Apr 1, 2008·6 cites·10 claims
- 3359US8341588B2Semiconductor layer forming method and structureHERZL ROBERT D·Filed 2010·Granted Dec 25, 2012·1 cites·19 claims
- 3459US7729877B2Method and system for logic verification using mirror interfaceIBM·Filed 2007·Granted Jun 1, 2010·2 cites·4 claims
- 3559US7536496B2Method and apparatus for transmitting data in an integrated circuitIBM·Filed 2006·Granted May 19, 2009·2 cites·1 claims
- 3658US8181148B2Method for identifying and implementing flexible logic block logic for easy engineering changesHERZL ROBERT D·Filed 2008·Granted May 15, 2012·1 cites·17 claims
- 3757US9367493B2Method and system of communicating between peer processors in SoC environmentDEVINS ROBERT J·Filed 2005·Granted Jun 14, 2016·1 cites·25 claims
- 3853US5640339ACache memory including master and local word lines coupled to memory cellsIBM·Filed 1996·Granted Jun 17, 1997·22 cites·3 claims
- 3952US8140314B2Optimal bus operation performance in a logic simulation environmentDEVINS ROBERT J·Filed 2008·Granted Mar 20, 2012·0 cites·10 claims
- 4048US2012167022A1Method and device for identifying and implementing flexible logic block logic for easy engineering changesHERZL ROBERT D·Filed 2012·Application pending·0 cites
- 4147US8416900B2Method and circuit for dynamically changing the frequency of clock signalsMILTON DAVID WILLS·Filed 2009·Granted Apr 9, 2013·0 cites·8 claims
- 4247US7065602B2Circuit and method for pipelined insertionIBM·Filed 2003·Granted Jun 20, 2006·0 cites·27 claims
- 4346US2009045839A1Asic logic library of flexible logic blocks and method to enable engineering changeIBM·Filed 2007·Application pending·0 cites
- 4446US2008276034A1Design Structure for Transmitting Data in an Integrated CircuitHARDING W RIYON·Filed 2008·Application pending·0 cites
- 4545US2009045836A1Asic logic library of flexible logic blocks and method to enable engineering changeHERZL ROBERT D·Filed 2007·Application pending·0 cites
- 4644US8300752B2Method, circuit, and design structure for capturing data across a pseudo-synchronous interfaceBERHANU MALEDE W·Filed 2008·Granted Oct 30, 2012·0 cites·15 claims
- 4744US2006047939A1Method and apparatus for initializing multiple processors residing in an integrated circuitIBM·Filed 2004·Application pending·0 cites
- 4844US2007204246A1Method and system for logic verification using mirror interfaceIBM·Filed 2007·Application pending·0 cites
- 4943US7863949B2Circuit and design structure for synchronizing multiple digital signalsIBM·Filed 2010·Granted Jan 4, 2011·0 cites·20 claims
- 5041US5717648AFully integrated cache architectureIBM·Filed 1995·Granted Feb 10, 1998·11 cites·11 claims
Showing the top 50 of 54 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →