Asic logic library of flexible logic blocks and method to enable engineering change

Abstract

A chip design methodology and an integrated circuit chip. The methodology includes providing a plurality of logic gates in a net list, wherein each of the logic gates comprises at least one spare input, synthesizing the net list, and connecting the spare inputs for performing an engineering change late in the design process. The invention is also directed to a design structure on which a circuit resides.

1 . A design structure embodied in a machine readable medium for designing, manufacturing, or testing a design, the design structure comprising:
 synthesized gate logic composed of a plurality of gates, in which each gate has an associated function; and   at least one flexible logic block arranged to replace at least one of the plurality of gates,   wherein the at least one flexible logic block is wired to perform the associated function of at least one of the plurality of gates replaced and includes at least one unused input.   
   
   
       2 . The design structure of  claim 1 , wherein the design structure comprises a netlist, which describes the circuit. 
   
   
       3 . The design structure of  claim 1 , wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits. 
   
   
       4 . The design structure of  claim 1 , wherein the design structure includes at least one of test data files, characterization data, verification data, or design specifications. 
   
   
       5 . A design structure embodied in a machine readable medium for designing, manufacturing, or testing a design, the design structure comprising:
 means for providing a plurality of logic gates in a net list, wherein each of the logic gates comprises at least one spare input;   means for synthesizing the net list; and   means for connecting the spare inputs for performing an engineering change late in the design process.