Inventor · disambiguated record
Nitin Sharma
Also filed as: SHARMA NITIN · SHARMA NITIN B
16 granted patents·7 pending applications·110 citations·filing 2003–2018
90Inventor score
Top patents by PatentIndex Score
23 records- 0197US7558539B2Power control feedback loop for adjusting a magnitude of an output signalFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Jul 7, 2009·69 cites·17 claims
- 0285US7480888B1Design structure for facilitating engineering changes in integrated circuitsIBM·Filed 2008·Granted Jan 20, 2009·14 cites·3 claims
- 0371US7546559B2Method of optimization of clock gating in integrated circuit designsATRENTA INC·Filed 2006·Granted Jun 9, 2009·6 cites·33 claims
- 0469US10311192B2System and method for power verification using efficient merging of power state tablesSYNOPSYS INC·Filed 2015·Granted Jun 4, 2019·2 cites·20 claims
- 0569US9100282B1Generating optimal pathways in software-defined networking (SDN)RAPS YARON·Filed 2014·Granted Aug 4, 2015·6 cites·13 claims
- 0668US8060845B2Minimizing impact of design changes for integrated circuit designsHERZL ROBERT D·Filed 2008·Granted Nov 15, 2011·4 cites·6 claims
- 0767US8141028B2Structure for identifying and implementing flexible logic block logic for easy engineering changesHERZL ROBERT D·Filed 2008·Granted Mar 20, 2012·4 cites·2 claims
- 0861US7715995B2Design structure for measurement of power consumption within an integrated circuitIBM·Filed 2008·Granted May 11, 2010·3 cites·11 claims
- 0959US8341588B2Semiconductor layer forming method and structureHERZL ROBERT D·Filed 2010·Granted Dec 25, 2012·1 cites·19 claims
- 1058US8181148B2Method for identifying and implementing flexible logic block logic for easy engineering changesHERZL ROBERT D·Filed 2008·Granted May 15, 2012·1 cites·17 claims
- 1150US10733342B2System and method for hierarchical power verificationSYNOPSYS INC·Filed 2018·Granted Aug 4, 2020·0 cites·20 claims
- 1248US2012167022A1Method and device for identifying and implementing flexible logic block logic for easy engineering changesHERZL ROBERT D·Filed 2012·Application pending·0 cites
- 1346US2009045839A1Asic logic library of flexible logic blocks and method to enable engineering changeIBM·Filed 2007·Application pending·0 cites
- 1445US6947391B2Method of optimizing a networkMOTOROLA INC·Filed 2003·Granted Sep 20, 2005·0 cites·36 claims
- 1545US6922398B2Optimized switch cardMOTOROLA INC·Filed 2003·Granted Jul 26, 2005·0 cites·24 claims
- 1645US2009045836A1Asic logic library of flexible logic blocks and method to enable engineering changeHERZL ROBERT D·Filed 2007·Application pending·0 cites
- 1744US7362840B2Circuit and method for adjusting timing alignment using programmable codesFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Apr 22, 2008·0 cites·20 claims
- 1842US2017011138A1System and method for hierarchical power verificationSYNOPSYS INC·Filed 2015·Application pending·0 cites
- 1941US7903493B2Design structure for estimating and/or predicting power cycle length, method of estimating and/or predicting power cycle length and circuit thereofIBM·Filed 2008·Granted Mar 8, 2011·0 cites·20 claims
- 2039US7228120B2Circuit and method for reducing direct current biasesFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Jun 5, 2007·0 cites·23 claims
- 2139US2009157334A1Measurement of power consumption within an integrated circuitGOODNOW KENNETH JOSEPH·Filed 2007·Application pending·0 cites
- 2234US2007063883A1Pipelined analog to digital converterFREESCALE SEMICONDUCTOR INC·Filed 2005·Application pending·0 cites
- 2326US2015312215A1Generating optimal pathways in software-defined networking (sdn)KHER LOV·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →