Inventor

KOTECHA HARISH N

21 patents

⚠️ This page may combine multiple inventors who share the name “KOTECHA HARISH N”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KOTECHA HARISH N

IBM

Electrically alterable double dense memory

Method of making a MOSFET device with reduced sensitivity of threshold voltage to source to substrate voltage variations

Multiple ROM data state, read/write memory cell

Resistor personalized memory device using a resistive gate fet

Two and three mask process for IGFET fabrication

Photoresist lift-off process for fabricating semiconductor devices

Integrated dynamic RAM and ROS

Low voltage electrically erasable programmable read only memory

Quaternary FET read only memory

Method for fabricating high circuit density, self-aligned metal linens to contact windows

Three terminal electrically erasable programmable read only memory

Simultaneously forming fully implanted DMOS together with enhancement and depletion mode MOSFET devices

Method of making ROM/PLA semiconductor device by late stage personalization

Non-volatile dynamic RAM cell

FET inverter with isolated substrate load

Non-volatile RAM cell with enhanced conduction insulators

Non-volatile static RAM cell with enhanced conduction insulators

Inverter with improved load line characteristic

Process for making a dual implanted drain extension for bucket brigade device tetrode structure

Method for providing increased dopant concentration in selected regions of semiconductor devices

US AIR FORCE

Two carrier dual injector apparatus