Multiple ROM data state, read/write memory cell

Abstract

A read/write memory cell is disclosed in which multiple ROM data states can be stored. Independent sensing of the resistance values of each of two resistors accounts for the storage of multiple ROM data states. The resistors are encompassed in a pair of cross-coupled resistive gate devices forming branch circuits, thereby allowing each branch circuit to control the conduction of current in the other branch circuit. This allows for read/write data storage in flip-flop-like fashion. In addition, since resistive gate devices are used, the ROM data may be programmed during the later stages of manufacturing.

What is claimed is: 
     
       1. A memory cell for storing a plurality of independent data states, each memory cell comprising: first and second branch circuits, each of said branch circuits having a resistive gate device and a resistive gate, one end of said resistive gate in each of said branch circuits coupled to a common cell access node, each of said branch circuits exhibiting an impedance characteristic of a predetermined electrical parameter within said branch circuit as a function of said resistive gate when said branch circuit is in its conductive state, the impedance characteristic of said first branch circuit being independent of the impedance characteristic of said second branch circuit, each value of the impedance characteristic corresponding to a different data state;   means within each branch circuit for controlling the conduction of current in the other branch circuit; and   means for sensing the impedance characteristic of each of said branch circuits to produce said different data states.   
     
     
       2. The memory cell of claim 1 wherein said first and second branch circuits comprise a pair of interconnected resistive gate devices, one end of the resistive gate of each of said devices serially connected to the drain of the other of said devices, the other end of the resistive gate of each of said devices connected to a common word line, the sources of said devices each connected to a different bit line. 
     
     
       3. The memory cell of claim 2 further comprising a separately gated device coupling the capacitance of one of the internal nodes of said memory cell to a third bit line.