Inventor

REBOH SHAY

FR66 patents

⚠️ This page may combine multiple inventors who share the name “REBOH SHAY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

REBOH SHAY

COMMISSARIAT ENERGIE ATOMIQUE

Method for making superimposed transistors

Method of fabricating a FET transistor having a strained channel

Method for making a semiconductor device with nanowire and aligned external and internal spacers

Field effect transistor with reduced contact resistance

Method for fabricating a device with a tensile-strained NMOS transistor and a uniaxial compression strained PMOS transistor

Method for making a semiconductor device with a compressive stressed channel

Method for producing a semiconductor device with self-aligned internal spacers

Method for making a semiconductor device with self-aligned inner spacers

Method of fabrication of a semiconductor substrate having at least a tensilely strained semiconductor portion

Method of producing a channel structure formed from a plurality of strained semiconductor bars

Method for fabricating a transistor having a vertical channel having nano layers

Process for fabricating a field effect transistor having a coating gate

Method for patterning a thin film

Method for making a transistor in a stack of superimposed semiconductor layers

Local strain generation in an SOI substrate

Enhanced method of introducing a stress in a transistor channel by means of sacrificial sources/drain regions and gate replacement

Method to increase strain in a semiconductor region for forming a channel of the transistor

Method for causing tensile strain in a semiconductor film

Manufacturing process of an RF-SOI trapping layer substrate resulting from a crystalline transformation of a buried layer

Enhanced method of stressing a transistor channel zone

Method for doping source and drain regions of a transistor by means of selective amorphisation

Method of fabricating a transistor channel structure with uniaxial strain

Method for manufacturing a transistor in which the strain applied to the channel is increased

Recrystallization of source and drain blocks from above

Method of making a transistor having a source and a drain obtained by recrystallization of semiconductor

Manufacturing of silicon strained in tension on insulator by amorphisation then recrystallisation

Method for modifying the strain state of a block of a semiconducting material

Semiconductor divice having a carbon containing insulation layer formed under the source/drain

Electronic device including at least one nano-object

Method for fabricating an integrated circuit including a NMOS transistor and a PMOS transistor

Method of manufacturing of a field effect transistor having a junction aligned with spacers

Method for fabricating a field-effect transistor

Method for layer transfer with localised reduction of a capacity to initiate a fracture

Method of healing an implanted layer comprising a heat treatment prior to recrystallisation by laser annealing

Method for transferring a useful layer

Method for forming doped extension regions in a structure having superimposed nanowires

Semiconductor substrate polishing method

RF substrate structure and method of production

Low-temperature method for transfer and healing of a semiconductor layer

Method for fabricating a doped region of a microelectronic device

Method for manufacturing a doped zone of a microelectronic device

Transistor with superposed bars and double-gate structure

IBM

Optimizing junctions of gate all around structures with channel pull back

Stacked FET with bottom epi size control and wraparound backside contact

Creation of stress in the channel of a nanosheet transistor

Creation of stress in the channel of a nanosheet transistor

Backside diffusion break

COMMISSARIAT A LENERGIE ATOMIQUE ET AUX ENE ALT

Method for producing a strained semiconductor on insulator substrate

COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT

Method for producing strained semi-conductor blocks on the insulating layer of a semi-conductor on insulator substrate

SOITEC SILICON ON INSULATOR

Substrates including useful layers