Semiconductor divice having a carbon containing insulation layer formed under the source/drain

Abstract

An electronic device including at least first and second superimposed transistors comprises at least a substrate; a first transistor including a portion of a first nanowire forming a first channel, and first source and drain regions in contact with ends of the first nanowire portion; and a second transistor including a portion of a second nanowire forming a second channel and having a greater length than that of the first channel, and second source and drain regions in contact with ends of the second nanowire portion such that the second transistor is arranged between the substrate and the first transistor. A dielectric encapsulation layer covers at least the second source and drain regions and such that the first source and drain regions are arranged at least partly on the dielectric encapsulation layer, and forms vertical insulating portions extending between the first and second source and drain regions.

The invention claimed is: 
     
       1. An electronic device including at least first and second superimposed transistors, comprising at least:
 a substrate; 
 a first transistor including a portion of a first nanowire forming a first channel, and first source and drain regions in contact with ends of the portion of the first nanowire; 
 a second transistor including a portion of a second nanowire forming a second channel and having a greater length than that of the first channel, and second source and drain regions in contact with ends of the portion of the second nanowire, such that the second transistor is arranged between the substrate and the first transistor; and 
 a first dielectric encapsulation layer covering at least the second source and drain regions and such that the first source and drain regions are arranged at least partly on the first dielectric encapsulation layer, and forming vertical insulating portions extending between the first and second source and drain regions. 
 
     
     
       2. The electronic device according to  claim 1 , further comprising a portion of another nanowire having a length substantially equal to that of the portion of the first nanowire and forming a separating region between the channels of the first and second transistors. 
     
     
       3. The electronic device according to  claim 2 , wherein:
 a width of the portion of the first nanowire is smaller than a width of the portion of said another nanowire, and 
 a width of the portion of the said nanowire is smaller than a width of the portion of the second nanowire. 
 
     
     
       4. The electronic device according to  claim 1 , further comprising first inner dielectric spacers arranged around ends of the portion of the first nanowire, and wherein side faces of the first source and drain regions are in contact with the ends of the portion of the first nanowire and with the first inner dielectric spacers. 
     
     
       5. The electronic device according to  claim 4 , further comprising first outer dielectric spacers arranged above the first inner dielectric spacers. 
     
     
       6. The electronic device according to  claim 4 , wherein the first source and drain regions comprise side faces which are in contact, or partially in contact, with the ends of the portion of the first nanowire and with the first inner dielectric spacers. 
     
     
       7. Electronic device according to  claim 1 , further comprising second inner dielectric spacers arranged around ends of the portion of the second nanowire, and wherein side faces of the second source and drain regions are in contact with the ends of the portion of the second nanowire and with the second inner dielectric spacers. 
     
     
       8. The electronic device according to  claim 7 , further comprising second outer dielectric spacers arranged above the second inner dielectric spacers. 
     
     
       9. The electronic device according to  claim 7 , wherein the second source and drain regions comprise side faces which are in contact, or partially in contact, with the ends of the portion of the second nanowire and with the second inner dielectric spacers. 
     
     
       10. The electronic device according to  claim 1 , wherein the first and second transistors are of the FET or SET type. 
     
     
       11. The electronic device according to  claim 1 , further comprising electrical contacts electrically connected to each of the first and second source and drain regions and so that at least two of the electrical contacts are each connected to only one of the first and second source and drain regions. 
     
     
       12. The electronic device according to  claim 1 , wherein a width of the portion of the first nanowire is smaller than a width of the portion of the second nanowire. 
     
     
       13. The electronic device according to  claim 1 , wherein the first source and drain regions are n-doped, and the second source and drain regions are p-doped.