Inventor · disambiguated record
Mark V. Raymond
Also filed as: RAYMOND MARK · RAYMOND MARK V · RAYMOND MARK VICTOR
32 granted patents·5 pending applications·298 citations·filing 1997–2020
96Inventor score
Top patents by PatentIndex Score
37 records- 0197US9721889B1Middle of the line (MOL) metal contactsGLOBALFOUNDRIES INC·Filed 2016·Granted Aug 1, 2017·21 cites·20 claims
- 0296US6096127ATuneable dielectric films having low electrical lossesSUPERCONDUCTING CORE TECHNOLOG·Filed 1997·Granted Aug 1, 2000·156 cites·19 claims
- 0395US10157794B1Integrated circuit structure with stepped epitaxial regionGLOBALFOUNDRIES INC·Filed 2017·Granted Dec 18, 2018·13 cites·14 claims
- 0492US9947589B1Methods of forming a gate contact for a transistor above an active region and the resulting deviceGLOBALFOUNDRIES INC·Filed 2017·Granted Apr 17, 2018·8 cites·19 claims
- 0590US9147765B2FinFET semiconductor devices with improved source/drain resistance and methods of making sameXIE RUILONG·Filed 2012·Granted Sep 29, 2015·10 cites·19 claims
- 0687US7655550B2Method of making metal gate transistorsFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Feb 2, 2010·14 cites·19 claims
- 0786US9184263B2Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devicesGLOBALFOUNDRIES INC·Filed 2013·Granted Nov 10, 2015·7 cites·20 claims
- 0885US10283608B2Low resistance contacts to source or drain region of transistorGLOBALFOUNDRIES INC·Filed 2017·Granted May 7, 2019·4 cites·11 claims
- 0984US9142633B2Integrated circuits and methods for fabricating integrated circuits with silicide contacts on non-planar structuresGLOBALFOUNDRIES INC·Filed 2012·Granted Sep 22, 2015·7 cites·17 claims
- 1083US10204994B2Methods of forming a semiconductor device with a gate contact positioned above the active regionGLOBALFOUNDRIES INC·Filed 2017·Granted Feb 12, 2019·4 cites·18 claims
- 1183US6576967B1Semiconductor structure and process for forming a metal oxy-nitride dielectric layerMOTOROLA INC·Filed 2000·Granted Jun 10, 2003·28 cites·17 claims
- 1282US10580696B1Interconnects formed by a metal displacement reactionGLOBALFOUNDRIES INC·Filed 2018·Granted Mar 3, 2020·3 cites·20 claims
- 1380US11031484B2Silicided gate structuresGLOBALFOUNDRIES US INC·Filed 2019·Granted Jun 8, 2021·2 cites·20 claims
- 1478US10186599B1Forming self-aligned contact with spacer firstIBM·Filed 2017·Granted Jan 22, 2019·2 cites·17 claims
- 1572US10593593B2Methods, apparatus, and system for protecting cobalt formations from oxidation during semiconductor device formationGLOBALFOUNDRIES INC·Filed 2018·Granted Mar 17, 2020·1 cites·13 claims
- 1671US6518070B1Process of forming a semiconductor device and a semiconductor deviceMOTOROLA INC·Filed 2000·Granted Feb 11, 2003·14 cites·19 claims
- 1766US10854515B2Methods, apparatus, and system for protecting cobalt formations from oxidation during semiconductor device formationGLOBALFOUNDRIES INC·Filed 2020·Granted Dec 1, 2020·0 cites·18 claims
- 1859US8854067B2Circular transmission line methods compatible with combinatorial processing of semiconductorsJOSHI AMOL·Filed 2012·Granted Oct 7, 2014·1 cites·12 claims
- 1958US7683439B2Semiconductor device having a metal carbide gate with an electropositive element and a method of making the sameFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Mar 23, 2010·1 cites·9 claims
- 2057US11621333B2Gate contact structure for a transistor deviceGLOBALFOUNDRIES US INC·Filed 2019·Granted Apr 4, 2023·0 cites·14 claims
- 2157US10727308B2Gate contact structure for a transistorGLOBALFOUNDRIES INC·Filed 2019·Granted Jul 28, 2020·0 cites·20 claims
- 2254US10643894B2Surface area and Schottky barrier height engineering for contact trench epitaxyIBM·Filed 2017·Granted May 5, 2020·0 cites·16 claims
- 2354US10026693B2Method, apparatus, and system for MOL interconnects without titanium linerGLOBALFOUNDRIES INC·Filed 2017·Granted Jul 17, 2018·0 cites·8 claims
- 2452US10490641B2Methods of forming a gate contact structure for a transistorGLOBALFOUNDRIES INC·Filed 2017·Granted Nov 26, 2019·0 cites·20 claims
- 2552US9679807B1Method, apparatus, and system for MOL interconnects without titanium linerGLOBALFOUNDRIES INC·Filed 2015·Granted Jun 13, 2017·0 cites·15 claims
- 2650US10643893B2Surface area and Schottky barrier height engineering for contact trench epitaxyIBM·Filed 2016·Granted May 5, 2020·0 cites·20 claims
- 2750US10483363B2Methods of forming a gate contact structure above an active region of a transistorGLOBALFOUNDRIES INC·Filed 2017·Granted Nov 19, 2019·0 cites·20 claims
- 2850US10283372B2Interconnects formed by a metal replacement processGLOBALFOUNDRIES INC·Filed 2017·Granted May 7, 2019·0 cites·20 claims
- 2950US9859217B1Middle of the line (MOL) metal contactsGLOBALFOUNDRIES INC·Filed 2017·Granted Jan 2, 2018·0 cites·18 claims
- 3048US2015349069A1Finfet semiconductor devices with improved source/drain resistanceGLOBALFOUNDRIES INC·Filed 2015·Application pending·0 cites
- 3146US6743668B2Process for forming a metal oxy-nitride dielectric layer by varying the flow rate of nitrogen into the chamberMOTOROLA INC·Filed 2003·Granted Jun 1, 2004·2 cites·11 claims
- 3244US2016181380A1Semiconductor Device Metal-Insulator-Semiconductor Contacts with Interface Layers and Methods for Forming the SameINTERMOLECULAR INC·Filed 2014·Application pending·0 cites
- 3341US8652963B2MOSFET integrated circuit with uniformly thin silicide layer and methods for its manufactureYANG BIN·Filed 2011·Granted Feb 18, 2014·0 cites·19 claims
- 3439US9218975B2Methods of forming a replacement gate structure having a gate electrode comprised of a deposited intermetallic compound materialCHOI KISIK·Filed 2012·Granted Dec 22, 2015·0 cites·18 claims
- 3538US2019081145A1Contact to source/drain regions and method of forming sameGLOBALFOUNDRIES INC·Filed 2017·Application pending·0 cites
- 3638US2018308752A1Middle-of-line local interconnect structures with hybrid featuresGLOBALFOUNDRIES INC·Filed 2017·Application pending·0 cites
- 3736US2004087163A1Method for forming magnetic clad bit lineFiled 2002·Application pending·0 cites
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