Inventor

DENNISON CHARLES H

US254 patents

⚠️ This page may combine multiple inventors who share the name “DENNISON CHARLES H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DENNISON CHARLES H

MICRON TECHNOLOGY INC

Use of gate electrode workfunction to improve DRAM refresh

Semiconductor processing methods of forming stacked capacitors

Self-aligned process for making contacts to silicon substrates during the manufacture of integrated circuits therein

Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells

Integrated circuits comprising interconnecting plugs

Semiconductor processing methods of forming stacked capacitors

Fully planarized thin film transistor (TFT) and process to fabricate same

Semiconductor processing methods of forming stacked capacitors

Method of forming a bit line over capacitor array of memory cells

Method of producing a self-aligned contact penetrating cell plate

Method for fabrication of close-tolerance lines and sharp emission tips on a semiconductor wafer

Reduced mask CMOS process for fabricating stacked capacitor multi-megabit dynamic random access memories utilizing single etch stop layer for contacts

Optimized container stacked capacitor DRAM cell utilizing sacrificial oxide deposition and chemical mechanical polishing

Optimized container stacked capacitor DRAM cell utilizing sacrificial oxide deposition and chemical mechanical polishing

Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography

Use of gate electrode workfunction to improve DRAM refresh

Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells

Method of forming CMOS devices using independent thickness spacers in a split-polysilicon DRAM process

Fabrication of complementary n-channel and p-channel circuits (ICs) useful in the manufacture of dynamic random access memories (drams)

Method for making electrical contact with an active area through sub-micron contact openings and a semiconductor device

Method of making stacked E-cell capacitor DRAM cell

Method of making self aligned contacts to silicon substrates during the manufacture of integrated circuits

Methods of forming complementary metal oxide semiconductor (CMOS) integrated circuitry

Method for formation of a stacked capacitor

Silicon on insulator DRAM process utilizing both fully and partially depleted devices

Structures comprising transistor gates

Methods of forming portions of transistor structures, methods of forming array peripheral circuitry, and structures comprising transistor gates

Method of storing a temperature threshold in an integrated circuit, method of modifying operation of dynamic random access memory in response to temperature, programmable temperature sensing circuit and memory integrated circuit

Self-aligned process for making contacts to silicon substrates during the manufacture of integrated circuits therein

Semiconductor processing method of forming a contact pedestal, of forming a storage node of a capacitor

Method of forming dram circuitry on a semiconductor substrate

Method of forming CMOS integrated circuitry having halo regions

CMOS integrated circuitry with Halo and LDD regions

Method to thermally form hemispherical grain (HSG) silicon to enhance capacitance for application in high density DRAMs

Arrays of memory integrated circuitry

Semiconductor processing method of producing an isolated polysilicon lined cavity and a method of forming a capacitor

Process for manufacturing a ferroelectric dynamic/non-volatile memory array using a disposable layer above storage-node junction

MICRON SEMICONDUCTOR INC

Multi-pin stacked capacitor utilizing micro villus patterning in a container cell and method to fabricate same

Method for forming enhanced capacitance stacked capacitor structures using hemi-spherical grain polysilicon

Method of forming a bit line over capacitor array of memory cells

Split-polysilicon CMOS process for multi-megabit dynamic memories incorporating stacked container capacitor cells

Thin film transistor (TFT) loads formed in recessed plugs

Semiconductor electrical interconnection methods

OVONYX INC

Reduced area intersection between electrode and programming element

Utilizing atomic layer deposition for programmable device

Self-aligned memory cells and method for forming

Method to manufacture a phase change memory

INTEL CORP

Phase change memory device on a planar composite layer

Phase change memory

MICRON TECHNOLOGIES INC

Semiconductor processing methods of forming stacked capacitors