Semiconductor processing methods of forming stacked capacitors

Abstract

In one aspect of the invention, an insulative nitride oxidation barrier layer is provided over a cell polysilicon layer to a thickness of at least about 150 Angstroms. An insulating layer is provided above the nitride oxidation barrier layer, and an contact/container is etched therethrough and through dielectric and cell polysilicon layers. Such exposes edges of the cell polysilicon within the contact/container. The wafer is then exposed to an oxidizing ambient to oxidize the cell polysilicon exposed edges, with the nitride oxidation barrier layer during such oxidation exposure inhibiting oxidation of the outer surface of the cell polysilicon layer. In another aspect, a multi-container stacked capacitor construction has its containers defined or otherwise electrically isolated in a single CMP step. In another aspect, a combination etch stop/oxidation barrier layer or region is provided to enable exposure of a precise quantity of the outside walls of a stacked capacitor container.

We claim: 
     
       1. A method of forming a DRAM storage device over a substrate comprising: forming a storage capacitor over a substrate node location laterally adjacent a substrate area in which a bit line contact is to be formed, the substrate node location being received between a pair of conductive word lines, the storage capacitor having a cell plate layer having an exposed edge adjacent the substrate area in which the bit line contact is to be formed;   forming an oxidation barrier insulative layer over the cell plate layer, the oxidation barrier insulative layer having an outermost surface which is everywhere planar between the pair of conductive word lines;   removing cell plate layer exposed edge material to a degree sufficient to undercut the cell plate layer relative to material of the oxidation barrier insulative layer;   oxidizing the undercut cell plate layer, the oxidation barrier insulative layer serving to protect adjacent cell plate layer material during the oxidizing;   after the oxidizing, outwardly exposing the substrate and defining the area in which the bit line contact is to be formed; and   forming conductive material over the substrate and within the area defined by the exposing, the oxidized undercut cell plate layer being electrically insulated from the conductive material.   
     
     
       2. A method of forming a bit line contact in a DRAM storage device comprising: interposing an etch stop layer between insulative materials over a substrate node location with which electrical communication is desired, the substrate node location being received between a pair of conductive word lines, the etch stop layer having an outermost surface which is everywhere planar between the pair of conductive word lines;   etching a first of the insulative materials to expose the etch stop layer and responsive thereto, terminating the etching;   after the etching of the first of the insulative materials, etching at least portions of the planar etch stop layer between the conductive word lines and a second of the insulative materials to expose the substrate node location; and   forming conductive material over and in electrical communication with the exposed node location, the conductive material comprising a bit line contact.   
     
     
       3. The method of claim 2, wherein the insulative materials are of the same material type. 
     
     
       4. The method of claim 2 further comprising after etching the first insulative material and prior to etching the second insulative material, oxidizing only a portion of a cell plate layer. 
     
     
       5. The method of claim 2 wherein the etch stop layer is supported by the second insulative material. 
     
     
       6. The method of claim 2 further comprising: after etching the first insulative material and prior to etching the second insulative material, oxidizing only a portion of a cell plate layer; and   wherein the etch stop layer is supported elevationally outwardly of the conductive line by the second insulative material.   
     
     
       7. A method of forming a DRAM storage device comprising: forming a storage capacitor relative to a semiconductive substrate, the storage capacitor having a capacitor cell layer which extends over: a node location with which electrical communication is desired, the node location being defined between a pair of laterally spaced apart conductive lines, one of the conduct lines comprising an access transistor for the storage capacitor;   an etch stop layer which is disposed over the node location and some of at least one of the conductive lines, and which has an outermost surface which is everywhere planar between the pair of lines, and   insulative material which is disposed under the etch stop layer, at least some of the insulative material being disposed laterally adjacent and between the conductive lines;     etching capacitor cell layer portions over the node location to a degree sufficient to expose the etch stop layer;   removing portions of the etch stop layer and the insulative material thereunder and between the conductive lines to expose the node location; and   forming conductive material over the node location and in electrical communication therewith.   
     
     
       8. The method of claim 7, wherein the etch stop layer is disposed over both of the conductive lines. 
     
     
       9. The method of claim 7, wherein the etch stop layer has an outermost surface the entirety of which is disposed elevationally outwardly of the conductive line pair. 
     
     
       10. The method of claim 7, wherein the etching of the capacitor cell layer portions comprises anisotropically etching said portions. 
     
     
       11. The method of claim 7, wherein the etching of the capacitor cell layer portions comprises undercutting material of the capacitor cell layer relative to the etch stop layer and a capacitor dielectric layer. 
     
     
       12. A semiconductor processing method of forming a stacked capacitor on a semiconductor wafer, the method comprising the following steps: providing a first node for electrical connection with a capacitor plate;   providing a second node;   forming an underlying layer of insulating material atop the wafer;   forming a combination etch stop and oxidation barrier insulative layer over the underlying insulating layer, the combination layer being different in composition from the insulating material of the underlying layer;   forming an intermediate layer of insulating material over the combination layer, the insulating material of the intermediate layer being different in composition from the insulating material of the combination layer with the insulating material of the intermediate layer being selectively etchable relative to the insulating material of the combination layer;   etching a capacitor contact opening through the intermediate, combination and underlying insulating layers to the first node;   forming a capacitor storage node within the capacitor contact opening in electrical communication with the first node, the storage node having outer sidewall surfaces;   etching the intermediate insulating layer selectively relative to the capacitor storage node and combination layer, and using the combination layer as an etch stop during such etching to expose only a portion of the outer surfaces of the capacitor storage node sidewalls;   forming a capacitor dielectric layer over the outer sidewall surfaces of the capacitor storage node;   forming a cell electrically conductive oxidizable material layer over the capacitor dielectric layer, the cell layer having an outer surface;   forming an electrically insulative oxidation barrier layer over the cell layer;   forming an overlying layer of insulating material above the oxidation barrier layer;   forming a masking layer of the same material as the combination layer above the overlying layer, the masking layer being provided to a thickness which is greater than that of the combination layer;   etching a first opening over the second node through the overlying, oxidation barrier and cell layers using the combination layer as an etch stop during such first opening etching, the first opening having sidewalls, the first opening sidewalls including an exposed edge of the cell layer;   oxidizing the cell layer exposed edge, the oxidation barrier layer during such oxidation exposure inhibiting oxidation of the outer surface of the cell layer, the combination layer during such oxidation exposure inhibiting oxidation of the capacitor storage node;   etching the combination layer from within the first opening;   etching the underlying layer from within the first opening to outwardly expose the second node for electrical contact; and   forming electrically conductive material within the first opening.