P

Inventor

MURALI VENKATESAN

US49 patents
⚠️ This page may combine multiple inventors who share the name “MURALI VENKATESAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

25 patents
US6687427B2Feb 3, 2004

Optic switch

INTEL CORP297 citations99
US6650817B2Nov 18, 2003

Multi-level waveguide

INTEL CORP32 citations96
US5492235AFeb 20, 1996

Process for single mask C4 solder bump fabrication

INTEL CORP112 citations95
US5047367ASep 10, 1991

Process for formation of a self aligned titanium nitride/cobalt silicide bilayer

INTEL CORP138 citations95
US6331446B1Dec 18, 2001

Process for underfilling a controlled collapse chip connection (C4) integrated circuit package with an underfill material that is heated to a partial gel state

INTEL CORP25 citations92
US6219910B1Apr 24, 2001

Method for cutting integrated circuit dies from a wafer which contains a plurality of solder bumps

INTEL CORP20 citations92
US4966868AOct 30, 1990

Process for selective contact hole filling including a silicide plug

INTEL CORP49 citations91
US7066657B2Jun 27, 2006

Optical subassembly

INTEL CORP38 citations90
US6450699B1Sep 17, 2002

Photonic and electronic components on a shared substrate

INTEL CORP29 citations90
US6265300B1Jul 24, 2001

Wire bonding surface and bonding method

INTEL CORP35 citations89
US5567981AOct 22, 1996

Bonding pad structure having an interposed rigid layer

INTEL CORP40 citations89
US6819836B2Nov 16, 2004

Photonic and electronic components on a shared substrate with through substrate communication

INTEL CORP14 citations84
US7141448B2Nov 28, 2006

Controlled collapse chip connection (C4) integrated circuit package which has two dissimilar underfill materials

INTEL CORP17 citations83
US6248951B1Jun 19, 2001

Dielectric decal for a substrate of an integrated circuit package

INTEL CORP17 citations82
US6278185B1Aug 21, 2001

Semi-additive process (SAP) architecture for organic leadless grid array packages

INTEL CORP19 citations79
US7000434B2Feb 21, 2006

Method of creating an angled waveguide using lithographic techniques

INTEL CORP9 citations74
US6731843B2May 4, 2004

Multi-level waveguide

INTEL CORP9 citations74
US6633707B1Oct 14, 2003

Lithographically defined optic array

INTEL CORP8 citations74
US7095937B2Aug 22, 2006

Multi-level waveguide

INTEL CORP3 citations63
US6869882B2Mar 22, 2005

Method of creating a photonic via using deposition

INTEL CORP6 citations63
US6788836B2Sep 7, 2004

Multi-level waveguide

INTEL CORP2 citations63
US6650823B1Nov 18, 2003

Method of creating a photonic via using fiber optic

INTEL CORP5 citations63
US6928216B2Aug 9, 2005

Markings for aligning fiber optic bundle

INTEL CORP4 citations60
US6778727B2Aug 17, 2004

Optic switch

INTEL CORP0 citations52
US6636671B2Oct 21, 2003

Markings for aligning fiber optic bundle

INTEL CORP0 citations50

MERLIN SOLAR TECH INC

7 patents

MURALI VENKATESAN

6 patents

GTAT CORP

4 patents

PETTI CHRISTOPHER J

2 patents

HILALI MOHAMED M

1 patent

JOSHI MUKUL

1 patent

XILINX INC

1 patent

RAHMAN ARIFUR

1 patent

JDS UNIPHASE CORP

1 patent