Inventor

LIU CHI-WEN

TW266 patents

⚠️ This page may combine multiple inventors who share the name “LIU CHI-WEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIU CHI-WEN

TAIWAN SEMICONDUCTOR MFG CO LTD

FinFETs with strained well regions

Strained nanowire CMOS device and method of forming

FINFETs with wrap-around silicide and method forming the same

FinFETs with strained well regions

Vertical gate all around (VGAA) devices and methods of manufacturing the same

Wrap around silicide for FinFETs

Metal gate of gate-all-around transistor

Semiconductor device and manufacturing method thereof

FinFET gate structure and method for fabricating the same

Devices including gate spacer with gap or void and methods of forming the same

FinFET devices and methods of forming

Devices including gate spacer with gap or void and methods of forming the same

Devices including gate spacer with gap or void and methods of forming the same

Devices including gate spacer with gap or void and methods of forming the same

Integrated circuit structure and method with solid phase diffusion

Interconnection structure, fabricating method thereof, and semiconductor device using the same

FETs and methods of forming FETs

Semiconductor device and manufacturing method thereof

Metal gate scheme for device and methods of forming

Stacked gate-all-around FinFET and method forming the same

Strained nanowire CMOS device and method of forming

Semiconductor device and method of forming the same

FINFETs with wrap-around silicide and method forming the same

Interconnection structure, fabricating method thereof, and semiconductor device using the same

Field-effect transistors having contacts to 2D material active region

Wrap around silicide for FinFETs

Integrated circuit structure and method with solid phase diffusion

Method of forming FinFET device by adjusting etch selectivity of dielectric layer

TAIWAN SEMICONDUCTOR MFG

FinFET device and method of manufacturing same

MOS devices with strain buffer layer and methods of forming the same

Self-aligned method for forming dual gate thin film transistor (TFT) device

FinFET structure with different fin heights and method for forming the same

Metal gate stack having TaAlCN layer

Isolation structure of fin field effect transistor

Passivated and faceted for fin field effect transistor

FinFET with buried insulator layer and method for forming

FinFETs with strained well regions

Metal surface and film protection method to prolong Q-time after metal deposition

Method of forming a copper damascene structure comprising a recessed copper-oxide-free initial copper structure

Fin structure of semiconductor device

FinFETs and methods for forming the same

MRAM cell having shared configuration

Method and apparatus for copper film quality enhancement with two-step deposition

Post ECP multi-step anneal/H2 treatment to reduce film impurity

CMP process leaving no residual oxide layer or slurry particles

LIU CHI-WEN

FinFET device and method of manufacturing same

Multi-fin device and method of making same

NG JIN-AUN

Method of forming a variety of replacement gate types including replacement gate types on a hybrid semiconductor device

WANN CLEMENT HSINGJEN

Selective fin-shaping process using plasma doping and etching for 3-dimensional transistor applications

CHEN KEI-WEI

Method of forming barrier layer with reduced resistivity and improved reliability in copper damascene process