Interconnection structure, fabricating method thereof, and semiconductor device using the same

Abstract

A semiconductor device includes a semiconductor substrate, a contact region present in the semiconductor substrate, and a silicide present on a textured surface of the contact region. A plurality of sputter ions are present between the silicide and the contact region. Since the surface of the contact region is textured, the contact area provided by the silicide is increased accordingly, thus the resistance of a interconnection structure in the semiconductor device is reduced.

What is claimed is: 
     
       1. A semiconductor device comprising:
 a semiconductor substrate; 
 a contact region present in the semiconductor substrate, wherein the contact region comprises a textured surface; 
 a silicide present on the contact region; and 
 a plurality of sputter residues present between the silicide and the contact region. 
 
     
     
       2. The semiconductor device of  claim 1 , wherein the sputter residues are Argon (Ar) ions, Neon (Ne) ions, Krypton (Kr), or Xenon (Xe) ions. 
     
     
       3. The semiconductor device of  claim 1 , wherein the contact region is an epitaxy structure. 
     
     
       4. The semiconductor device of  claim 1 , wherein the contact region is a semiconductor pad. 
     
     
       5. The semiconductor device of  claim 1 , wherein an interface between the silicide and the contact region is irregular. 
     
     
       6. The semiconductor device of  claim 1 , further comprising a dielectric layer present on the semiconductor substrate, the dielectric layer comprising an opening to expose a portion of the silicide. 
     
     
       7. The semiconductor device of  claim 6 , further comprising:
 a conductor filling the opening; and 
 a barrier layer present on a sidewall of the opening and on the silicide. 
 
     
     
       8. The semiconductor device of  claim 7 , further comprising:
 a metal layer present between the sidewall of the opening and the barrier layer, wherein the metal layer is not present between the silicide and the barrier layer. 
 
     
     
       9. An interconnection structure comprising:
 a silside present on a contact region, wherein an interface between the contact region and the silicide is textured, and a plurality of sputter residues are present in the silicide; 
 a conductor present on the silicide; and 
 a barrier layer present between the conductor and the silicide. 
 
     
     
       10. The interconnection structure of  claim 9 , wherein the sputter residues comprises Argon (Ar) ions, Neon (Ne) ions, Krypton (Kr), or Xenon (Xe) ions. 
     
     
       11. The interconnection structure of  claim 9 , further comprising a metal layer, wherein the metal layer is present at a sidewall of the barrier layer and is not present between the silicide and the barrier layer. 
     
     
       12. The interconnection structure of  claim 11 , wherein the metal layer is made of titanium (Ti), cobalt (Co), nickel (Ni), platinum (Pt), or tungsten (W). 
     
     
       13. The interconnection structure of  claim 9 , wherein the barrier layer is made of tantalum (Ta), titanium (Ti). 
     
     
       14. The interconnection structure of  claim 9 , wherein the conductor is made of tungsten (W), copper (Cu), or cobalt (Co). 
     
     
       15. A method of fabricating an interconnection structure, the method comprising:
 forming an opening in a dielectric layer to expose a portion of a contact region; 
 performing a physical removal process to texture a surface of the contact region; 
 forming a metal layer on the textured surface of the contact region; 
 forming a barrier layer on the metal layer; and 
 performing an annealing process, wherein the metal layer is reacted with the contact region thereby forming a silicide between the contact region and the barrier layer. 
 
     
     
       16. The method of  claim 15 , wherein the physical removal process removes a portion of the oxide layer on the surface of the contact region, and the method further comprises performing a chemical removal process after the physical removal process to remove a residual portion of the oxide layer. 
     
     
       17. The method of  claim 15 , wherein the physical removal process forms a plurality of recesses on the surface of the contact region. 
     
     
       18. The method of  claim 15 , wherein the physical removal process comprises a sputter process. 
     
     
       19. The method of  claim 15 , wherein the annealing process is performed after the barrier layer is formed on the metal layer. 
     
     
       20. The method of  claim 15 , further comprising:
 forming a conductor on the barrier layer and filling the opening.