Inventor

BUYNOSKI MATTHEW

US27 patents

⚠️ This page may combine multiple inventors who share the name “BUYNOSKI MATTHEW”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BUYNOSKI MATTHEW

ADVANCED MICRO DEVICES INC

Method of making a self-aligned triple gate silicon-on-insulator device

Self-aligned double gate silicon-on-insulator (SOI) device

Method for increasing gate capacitance by using both high and low dielectric gate material

Practical way to remove heat from SOI devices

Silicide gate transistors

Semiconductor device having enhanced gate capacitance by using both high and low dielectric materials

Self-aligned triple gate silicon-on-insulator (SOI) device

Method of copper-polysilicon T-gate formation

Tantalum anodization for in-laid copper metallization capacitor

Metal silicide gate transistors

Selectively thin silicon film for creating fully and partially depleted SOI on same wafer

Heat removal from SOI devices by using metal substrates

Methods for fabricating CMOS-compatible lateral bipolar junction transistors

Method for manufacturing CMOS device having low gate resistivity using aluminum implant

Method providing, an enriched source side extension and a lightly doped extension

Method for reducing stress-induced voids for 0.25mμ and smaller semiconductor chip technology by annealing interconnect lines and using low bias voltage and low interlayer dielectric deposition rate and semiconductor chip made thereby

Integration scheme for non-feature-size dependent cu-alloy introduction

METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25-μM AND SMALLER SEMICONDUCTOR CHIP TECHNOLOGY BY ANNEALING INTERCONNECT LINES AND USING LOW BIAS VOLTAGE AND LOW INTERLAYER DIELECTRIC DEPOSITION RATE AND SEMICONDUCTOR CHIP MADE THEREBY

SPANSION LLC

Diode array architecture for addressing nanoscale resistive memory arrays

Test structures for development of metal-insulator-metal (MIM) devices

Thin film germanium diode with low reverse breakdown

CYPRESS SEMICONDUCTOR CORP

Method of forming controllably conductive oxide

Method of forming controllably conductive oxide

NAT SEMICONDUCTOR CORP

Self-aligned masking for ultra-high energy implants with application to localized buried implants and insolation structures

RATHOR MANUJ

Gettering/stop layer for prevention of reduction of insulating oxide in metal-insulator-metal device

BUYNOSKI MATTHEW

Method of forming controllably conductive oxide

AVANZINO STEVEN

Test structures for development of metal-insulator-metal (MIM) devices