Inventor
YANG DEOKKYUNG
KR50 patents
⚠️ This page may combine multiple inventors who share the name “YANG DEOKKYUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
STATS CHIPPAC PTE LTD
25 patentsUS10636765B2Apr 28, 2020
System-in-package with double-sided molding
STATS CHIPPAC PTE LTD24 citations93
US11189598B2Nov 30, 2021
Semiconductor device and method of forming embedded die substrate, and system-in-package modules with the same
STATS CHIPPAC PTE LTD7 citations84
US10937741B2Mar 2, 2021
Molded laser package with electromagnetic interference shield and method of making
STATS CHIPPAC PTE LTD10 citations84
US10797039B2Oct 6, 2020
Semiconductor device and method of forming a 3D interposer system-in-package module
STATS CHIPPAC PTE LTD6 citations84
US10636774B2Apr 28, 2020
Semiconductor device and method of forming a 3D integrated system-in-package module
STATS CHIPPAC PTE LTD5 citations84
US10468384B2Nov 5, 2019
Semiconductor device and method of forming embedded die substrate, and system-in-package modules with the same
STATS CHIPPAC PTE LTD7 citations84
US10388637B2Aug 20, 2019
Semiconductor device and method of forming a 3D interposer system-in-package module
STATS CHIPPAC PTE LTD8 citations84
US9997468B2Jun 12, 2018
Integrated circuit packaging system with shielding and method of manufacturing thereof
STATS CHIPPAC PTE LTD5 citations84
US10797024B2Oct 6, 2020
System-in-package with double-sided molding
STATS CHIPPAC PTE LTD6 citations83
US10700011B2Jun 30, 2020
Semiconductor device and method of forming an integrated SIP module with embedded inductor or package
STATS CHIPPAC PTE LTD7 citations83
US11670618B2Jun 6, 2023
System-in-package with double-sided molding
STATS CHIPPAC PTE LTD2 citations72
US10636756B2Apr 28, 2020
Semiconductor device and method of forming protrusion E-bar for 3D SIP
STATS CHIPPAC PTE LTD4 citations70
US10083903B1Sep 25, 2018
Integrated circuit packaging system with molded laser via interposer and method of manufacture thereof
STATS CHIPPAC PTE LTD1 citations63
US12046564B2Jul 23, 2024
Method and device for reducing metal burrs when sawing semiconductor packages
STATS CHIPPAC PTE LTD0 citations62
US11842991B2Dec 12, 2023
Semiconductor device and method of forming a 3D interposer system-in-package module
STATS CHIPPAC PTE LTD0 citations62
US11676911B2Jun 13, 2023
Method and device for reducing metal burrs when sawing semiconductor packages
STATS CHIPPAC PTE LTD0 citations62
US11652088B2May 16, 2023
Semiconductor device and method of forming embedded die substrate, and system-in-package modules with the same
STATS CHIPPAC PTE LTD0 citations62
US11244908B2Feb 8, 2022
Method and device for reducing metal burrs when sawing semiconductor packages
STATS CHIPPAC PTE LTD0 citations62
US11145603B2Oct 12, 2021
Integrated circuit packaging system with shielding and method of manufacture thereof
STATS CHIPPAC PTE LTD0 citations62
US11024585B2Jun 1, 2021
Integrated circuit packaging system with shielding and method of manufacture thereof
STATS CHIPPAC PTE LTD0 citations62
US12266614B2Apr 1, 2025
Molded laser package with electromagnetic interference shield and method of making
STATS CHIPPAC PTE LTD0 citations61
US11587882B2Feb 21, 2023
Molded laser package with electromagnetic interference shield and method of making
STATS CHIPPAC PTE LTD0 citations61
US11367690B2Jun 21, 2022
Semiconductor device and method of forming an integrated SiP module with embedded inductor or package
STATS CHIPPAC PTE LTD0 citations61
US11342294B2May 24, 2022
Semiconductor device and method of forming protrusion e-bar for 3D SiP
STATS CHIPPAC PTE LTD0 citations60
US10790268B2Sep 29, 2020
Semiconductor device and method of forming a 3D integrated system-in-package module
STATS CHIPPAC PTE LTD0 citations52
YOON IN SANG
5 patentsUS8765525B2Jul 1, 2014
Method of manufacturing an integrated circuit packaging system including lasering through encapsulant over interposer
YOON IN SANG8 citations84
US9385066B1Jul 5, 2016
Integrated circuit packaging system with molded laser via interposer and method of manufacture thereof
YOON IN SANG4 citations73
US8497575B2Jul 30, 2013
Semiconductor packaging system with an aligned interconnect and method of manufacture thereof
YOON IN SANG6 citations73
US9905491B1Feb 27, 2018
Interposer substrate designs for semiconductor packages
YOON IN SANG5 citations72
US8247894B2Aug 21, 2012
Integrated circuit package system with step mold recess
YOON IN SANG6 citations72
YANG DEOKKYUNG
5 patentsUS8518752B2Aug 27, 2013
Integrated circuit packaging system with stackable package and method of manufacture thereof
YANG DEOKKYUNG8 citations83
US8067306B2Nov 29, 2011
Integrated circuit packaging system with exposed conductor and method of manufacture thereof
YANG DEOKKYUNG11 citations82
US8633100B2Jan 21, 2014
Method of manufacturing integrated circuit packaging system with support structure
YANG DEOKKYUNG6 citations72
US9748203B2Aug 29, 2017
Integrated circuit packaging system with conductive pillars and method of manufacture thereof
YANG DEOKKYUNG3 citations71
US8603859B2Dec 10, 2013
Integrated circuit packaging system with dual side mold and method of manufacture thereof
YANG DEOKKYUNG1 citations51
STATS CHIPPAC LTD
4 patentsUS7859099B2Dec 28, 2010
Integrated circuit packaging system having through silicon via with direct interconnects and method of manufacture thereof
STATS CHIPPAC LTD6 citations72
US7994625B2Aug 9, 2011
Integrated circuit packaging system having an internal structure protrusion and method of manufacture thereof
STATS CHIPPAC LTD2 citations60
US7875967B2Jan 25, 2011
Integrated circuit with step molded inner stacking module package in package system
STATS CHIPPAC LTD0 citations52
US7687920B2Mar 30, 2010
Integrated circuit package-on-package system with central bond wires
STATS CHIPPAC LTD1 citations51
PARK HYUNGSANG
2 patentsCHOI A LEAM
2 patentsUS8699232B2Apr 15, 2014
Integrated circuit packaging system with interposer and method of manufacture thereof
CHOI A LEAM1 citations50
US8093100B2Jan 10, 2012
Integrated circuit packaging system having through silicon via with direct interconnects and method of manufacture thereof
CHOI A LEAM0 citations50