Semiconductor device and method of forming an integrated SiP module with embedded inductor or package

Abstract

A semiconductor device has a substrate with a first opening and second opening formed in the substrate. A first semiconductor component is disposed on the substrate. The substrate is disposed on a carrier. A second semiconductor component is disposed on the carrier in the first opening of the substrate. A third semiconductor component is disposed in the second opening. The third semiconductor component is a semiconductor package in some embodiments. A first shielding layer may be formed over the semiconductor package. An encapsulant is deposited over the substrate, first semiconductor component, and second semiconductor component. A shielding layer may be formed over the encapsulant.

What is claimed: 
     
       1. A semiconductor device, comprising:
 a substrate including a first opening formed in the substrate; 
 a first semiconductor component disposed on the substrate; 
 a discrete inductor comprising a first solder bump disposed in the first opening of the substrate; 
 an encapsulant deposited over the substrate, first semiconductor component, and discrete inductor, wherein the encapsulant contacts the first solder bump and the first solder bump is exposed from the encapsulant; and 
 a second solder bump disposed on the first solder bump outside the encapsulant. 
 
     
     
       2. The semiconductor device of  claim 1 , further including:
 a second opening formed in the substrate; and 
 a second semiconductor component disposed in the second opening. 
 
     
     
       3. The semiconductor device of  claim 2 , wherein the second semiconductor component is a semiconductor package. 
     
     
       4. The semiconductor device of  claim 3 , further including a first shielding layer formed over the semiconductor package, wherein the encapsulant is deposited over the first shielding layer. 
     
     
       5. The semiconductor device of  claim 4 , further including a second shielding layer formed over the encapsulant, wherein the second shielding layer contacts a side surface of the substrate and the side surface of the substrate is perpendicular to the bottom surface of the substrate. 
     
     
       6. The semiconductor device of  claim 1 , wherein a distance from a top surface of the encapsulant to a top surface of the substrate is less than a height of the discrete inductor. 
     
     
       7. A semiconductor device, comprising:
 a substrate including an opening formed in the substrate; 
 a first semiconductor component disposed in the opening of the substrate, wherein the first semiconductor component includes a first solder bump; 
 an encapsulant deposited over the substrate and first semiconductor component, wherein the encapsulant contacts and surrounds the first solder bump; and 
 a second solder bump disposed on the first solder bump outside the encapsulant. 
 
     
     
       8. The semiconductor device of  claim 7 , further including:
 a second opening formed in the substrate; and 
 an electrical component disposed in the second opening. 
 
     
     
       9. The semiconductor device of  claim 7 , further including a shielding layer formed over the encapsulant. 
     
     
       10. The semiconductor device of  claim 9 , further including:
 a second opening formed in the substrate; and 
 a semiconductor package disposed in the second opening. 
 
     
     
       11. The semiconductor device of  claim 10 , further including a second shielding layer formed over the semiconductor package. 
     
     
       12. A semiconductor device, comprising:
 a substrate including a first opening formed in the substrate; 
 a first semiconductor component disposed on the substrate; 
 a second semiconductor component disposed in the first opening of the substrate, wherein the second semiconductor component includes an interconnect structure, and wherein the interconnect structure is a contact pad or solder bump; and 
 an encapsulant disposed over the substrate, first semiconductor component, and second semiconductor component, wherein the encapsulant contacts and surrounds the interconnect structure while the interconnect structure remains exposed from the encapsulant. 
 
     
     
       13. The semiconductor device of  claim 12 , wherein a distance from a top surface of the encapsulant to a top surface of the first substrate is less than a height of the second semiconductor component. 
     
     
       14. The semiconductor device of  claim 12 , further including a shielding layer disposed over the encapsulant. 
     
     
       15. The semiconductor device of  claim 12 , wherein the second semiconductor component is a semiconductor package. 
     
     
       16. The semiconductor device of  claim 12 , further including a third semiconductor component, wherein the first substrate further includes a second opening with the third semiconductor component disposed in the second opening. 
     
     
       17. The semiconductor device of  claim 12 , further including a third semiconductor component disposed in the first opening. 
     
     
       18. A semiconductor device, comprising:
 a substrate; 
 a first semiconductor component disposed over the substrate; and 
 a second semiconductor component disposed adjacent to the substrate, wherein the second semiconductor component includes a solder bump or contact pad; and 
 an encapsulant deposited over the substrate and contacting the solder bump or contact pad, wherein the solder bump or contact pad remains exposed from the encapsulant. 
 
     
     
       19. The semiconductor device of  claim 18 , wherein a height of the second semiconductor component is greater than a height of the first semiconductor component. 
     
     
       20. The semiconductor device of  claim 18 , further including a semiconductor package disposed adjacent to the substrate. 
     
     
       21. The semiconductor device of  claim 20 , further including a shielding layer formed over the semiconductor package. 
     
     
       22. The semiconductor device of  claim 18 , wherein the second semiconductor component is disposed within an opening of the substrate. 
     
     
       23. The semiconductor device of  claim 18 , further including a tape laminated on the substrate opposite the first semiconductor component, wherein the second semiconductor component is disposed on the tape.