P
US9748203B2ActiveUtilityPatentIndex 71

Integrated circuit packaging system with conductive pillars and method of manufacture thereof

Assignee: YANG DEOKKYUNGPriority: Dec 15, 2011Filed: Dec 15, 2011Granted: Aug 29, 2017
Est. expiryDec 15, 2031(~5.5 yrs left)· nominal 20-yr term from priority
Inventors:YANG DEOKKYUNGYOON IN SANGMUN SEONGHUNKIM KYUNGHWAN
H10W 90/736H10W 90/734H10W 90/732H10W 90/726H10W 90/724H10W 90/722H10W 90/284H10W 74/142H10W 74/117H10W 74/15H10W 72/877H10W 72/20H10W 90/28H10W 90/00H01L 2225/06513H01L 25/0657H01L 2924/15311H01L 24/16H01L 24/32H01L 2224/32145H01L 2224/73204H01L 2224/32245H01L 2924/19107H01L 2224/16145H01L 2225/06517H01L 2224/73253H01L 2224/16245H01L 23/3128H01L 2924/00H01L 2225/06596H01L 2924/18161H01L 24/13H01L 2224/16225H01L 2924/00012H01L 24/73H01L 2224/32225
71
PatentIndex Score
3
Cited by
17
References
10
Claims

Abstract

A method of manufacture of an integrated circuit packaging system including: providing a package carrier; mounting an integrated circuit to the package carrier; mounting a circuit interposer above the integrated circuit; mounting a mounting integrated circuit above the circuit interposer; forming a conductive pillar to the circuit interposer adjacent to the mounting integrated circuit; connecting the circuit interposer to the package carrier; and forming an encapsulation on the package carrier.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. An integrated circuit packaging system comprising:
 a package carrier; 
 a first integrated circuit mounted to the package carrier; 
 an underfill between the package carrier and the first integrated circuit; 
 a circuit interposer mounted above the first integrated circuit and connected to the package carrier, wherein the circuit interposer is an integrated passive device or an active device; 
 a second integrated circuit mounted above the circuit interposer; 
 a conductive pillar formed to the circuit interposer adjacent to the second integrated circuit; and 
 an encapsulation formed on the package carrier and the second integrated circuit, a non-active side of the second integrated circuit exposed from and coplanar with a horizontal surface of the encapsulation; and 
 wherein a top surface of the conductive pillar is below a top surface of the second integrated circuit, and the top surface of the conductive pillar and the top surface of the second integrated circuit are exposed from the encapsulation. 
 
     
     
       2. The system as claimed in  claim 1  further comprising interposer electrical connectors between the first integrated circuit and the package carrier. 
     
     
       3. The system as claimed in  claim 1  further comprising solder balls between the circuit interposer and the package carrier. 
     
     
       4. The system as claimed in  claim 1  wherein the conductive pillar is at a level planar with the top of the encapsulation. 
     
     
       5. The system as claimed in  claim 1  wherein the conductive pillar formed to the circuit interposer is at a level planar with a surface of the encapsulation and below a non-active surface of the second integrated circuit. 
     
     
       6. The system as claimed in  claim 1  wherein the circuit interposer mounted above the first integrated circuit is an integrated circuit interposer. 
     
     
       7. The system as claimed in  claim 6  wherein the circuit interposer mounted above the first integrated circuit is electrically connected to the package carrier with bond wire interposer electrical connectors. 
     
     
       8. The system as claimed in  claim 6  wherein the circuit interposer mounted above the first integrated circuit is electrically connected to the package carrier with solder balls. 
     
     
       9. The system as claimed in  claim 6  wherein the conductive pillar formed to the circuit interposer includes the conductive pillar at a level planar with the top of the encapsulation. 
     
     
       10. The system as claimed in  claim 6  wherein the conductive pillar formed to the circuit interposer is at a level planar with a surface of the encapsulation and below a non-active surface of the second integrated circuit.

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