Inventor

HOENIGSCHMID HEINZ

US83 patents

⚠️ This page may combine multiple inventors who share the name “HOENIGSCHMID HEINZ”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HOENIGSCHMID HEINZ

INFINEON TECHNOLOGIES AG

Serial MRAM device

Integrated semiconductor memory with redundant units for memory cells

Data memory with a plurality of memory banks

Non-orthogonal MRAM device

Semiconductor memory configuration with a refresh logic circuit, and method of refreshing a memory content of the semiconductor memory configuration

MRAM memory cell

Integrated memory having a differential sense amplifier

Circuit configuration for controlling write and read operations in a magnetoresistive memory configuration

Fuse concept and method of operation

Magnetoresistive memory (MRAM)

Narrow contact design for magnetic random access memory (MRAM) arrays

Methods for generating a reference voltage and for reading a memory cell and circuit configurations implementing the methods

Using FeRam/MRAM cells having a high degree of flexibility and compact construction and method of operating the memory device

Integrated magnetoresistive semiconductor memory and fabrication method for the memory

Ferroelectric memory configuration and a method for producing the configuration

Fuse circuit configuration

Circuit configuration for generating a reference voltage for reading a ferroelectric memory

Integrated memory having cells of the two-transistor/two-capacitor type

Ferroelectric memory configuration

Memory circuit including a resistive memory element and method for operating such a memory circuit

Method and memory circuit for operating a resistive memory cell

Method for fabricating a ferroelectric memory configuration

Integrated circuit memory having a read circuit

Memory device and method for operating such a memory device

MRAM configuration having selection transistors with a large channel width

Circuit configuration and method for accelerating aging in an MRAM

Integrated memory with plate line segments

Integrated memory having memory cells and reference cells, and operating method for such a memory

Semiconductor circuit configuration

Integrated memory having memory cells and reference cells, and corresponding operating method

Circuit configuration for reading a memory cell having a ferroelectric capacitor

Ferroelectric memory array composed of a multiplicity of memory cells each having at least one selection transistor and one storage capacitor driven via word lines and bit lines

Integrated memory

IBM

Dummy feature reduction using optical proximity effect correction

Error detection and correction method and apparatus in a magnetoresistive random access memory

DRAM cell with transfer device extending along perimeter of trench storage capacitor

Magnetic tunnel junction memory cell architecture

Wordline driver circuit using ring-shaped devices

Ultra compact DRAM cell and method of making

SIEMENS AG

Semiconductor memory having hierarchical bit line architecture with non-uniform local bit lines

High density semiconductor memory having diagonal bit lines and dual word lines

Space-efficient semiconductor memory having hierarchical column select line architecture

Reduced stand by power consumption in a DRAM

Dynamic random access memory arrays and methods therefor

Ferroelectric memory and method for preventing aging in a memory cell

INFINEON TECHNOLOGIES CORP

Reference for MRAM cell

QIMONDA AG

Method of determining a memory state of a resistive memory cell and device measuring the memory state of a resistive memory cell

QIMODA AG

Integrated circuit, memory chip and method of evaluating a memory state of a resistive memory cell

KUND MICHAEL

Memory scheduler for managing maintenance operations in a resistive memory in response to a trigger condition

MICRON TECHNOLOGY INC

Memory health status reporting