Ferroelectric memory configuration and a method for producing the configuration

Abstract

An integrated ferroelectric memory configuration and a method for producing the integrated ferroelectric memory configuration, in which memory cells are arranged using the stacking principle, and both capacitor electrodes, which are located one above the other, of each memory cell are directly electrically connected by means of contact plugs to corresponding source and drain regions of an associated selection transistor in the substrate. Contact plugs for the contact connection to the upper capacitor electrodes are produced from above the configuration.

We claim:  
     
       1. A method for producing an integrated ferroelectric memory configuration, which comprises: 
       configuring memory cells using a stacking principle;  
       for each one of the memory cells, providing a capacitor having two capacitor electrodes located one above another and providing an associated selection transistor located in a substrate below the capacitor;  
       for each one of the memory cells, providing contact plugs to directly electrically connect the two capacitor electrodes to a source region and a drain region of the associated selection transistor;  
       producing given ones of the contact plugs from above;  
       in a first step, for the capacitor of each one of the memory cells, first producing one of the contact plugs for a lower one of the capacitor electrodes and then producing a dielectric;  
       in a second step, for the capacitor of each one of the memory cells, etching a contact hole from above, through the upper one of the capacitor electrodes and at least through the dielectric as far as a substrate area of the associated selection transistor, the contact hole being for one of the given ones of the contact plugs for contact connecting an upper one of the capacitor electrodes; and  
       in a third step, for the capacitor of each one of the memory cells, producing the one of the given ones of the contact plugs from above by filling the contact hole with a highly conductive metallic material to form an electrically conductive connection between the upper one of the capacitor electrodes and the substrate area of the associated selection transistor.  
     
     
       2. The production method according to  claim 1 , which comprises: 
       in the second step, also etching the contact hole through the lower capacitor electrode; and  
       in the third step, before the contact hole is filled with the metallic material, forming an insulating spacing layer on a wall of the contact hole at least around an exposed area of the lower one of the capacitor electrodes to insulate the lower one of the capacitor electrodes from the one of the given ones of the contact plugs.  
     
     
       3. The production method according to  claim 1 , which comprises: 
       in the first step, for the capacitor of each one of the memory cells, forming the upper one of the capacitor electrodes and the dielectric to overlap the lower one of the capacitor electrodes in the contact hole such that the dielectric provides electrical insulation between the upper one of the capacitor electrodes and the lower one of the capacitor capacitor electrodes.