Inventor

LIU YAUH-CHING

US65 patents

⚠️ This page may combine multiple inventors who share the name “LIU YAUH-CHING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIU YAUH-CHING

MICRON TECHNOLOGY INC

Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography

Method of making stacked E-cell capacitor DRAM cell

Method for formation of a stacked capacitor

EEPROM transistor for a DRAM

Capacitor structures, DRAM cell structures, methods of forming capacitors, methods of forming DRAM cells, and integrated circuits incorporating capacitor structures and DRAM cell structures

Method of making EEPROM transistor for a DRAM

Method of forming a field effect transistor

Lateral extension stacked capacitor

Method for increasing capacitive surface area of a conductive material in semiconductor processing and stacked memory cell capacitor

Double DRAM cell

Method for forming low resistance DRAM digit-line

Method of making stacked textured container capacitor

Double DRAM cell

Process for creating field effect transistors having reduced-slope, staircase-profile sidewall spacers

Method for formation of a stacked capacitor

Process to fabricate a double ring stacked cell structure

EEPROM transistor for a DRAM

Method of making EEPROM transistor for a DRAM

Capacitor structures, DRAM cell structures, methods of forming capacitors, methods of forming DRAM cells, and integrated circuits incorporating capacitor structures and DRAM cell structures

DRAM stacked capacitor fabrication process

Method of making a stacked capacitor dram cell

Stacked v-cell capacitor using a disposable composite dielectric on top of a digit line

Semiconductor manufacturing process for decreasing the optical refelctivity of a metal layer

Mushroom double stacked capacitor

Method of making stacked surrounding reintrant wall capacitor

Enclosed ferroelectric stacked capacitor

Stacked delta cell capacitor

Approach to avoid buckling in BPSG by using an intermediate barrier layer

Approach to avoid buckling BPSG by using an intermediate barrier layer

Stacked V-cell capacitor using a disposable outer digit line spacer

LSI LOGIC CORP

Method of single step damascene process for deposition and global planarization

Method of single step damascene process for deposition and global planarization

DRAM cell having a vertical transistor and a capacitor formed on the sidewalls of a trench isolation

Integrated circuit having embedded memory with electromagnetic shield

Formation of novel DRAM cell capacitors by integration of capacitors with isolation trench sidewalls

Formation of novel DRAM cell capacitors by integration of capacitors with isolation trench sidewalls

Fuse construction for integrated circuit structure having low dielectric constant dielectric material

Method for simultaneous formation of integrated capacitor and fuse

Self-aligned fuse structure and method with heat sink

Silicide encapsulation of polysilicon gate and interconnect

DRAM cell having a verticle transistor and a capacitor formed on the sidewalls of a trench isolation

Self-aligned fuse structure and method with anti-reflective coating

Process for forming self-aligned metal silicide contacts for MOS structure using single silicide-forming step

Laser-breakable fuse link with alignment and break point promotion structures

Reduced soft error rate (SER) construction for integrated circuit structures

Fuse construction for integrated circuit structure having low dielectric constant dielectric material

Self-aligned fuse structure and method with dual-thickness dielectric

Metal-encapsulated polysilicon gate and interconnect

Single channel four transistor SRAM

MICRON SEMICONDUCTOR INC

Approach to avoid buckling in BPSG by using an intermediate barrier layer