DRAM stacked capacitor fabrication process

Abstract

This invention relates to semiconductor circuit memory storage devices and more particularly to a process to develop three-dimensional stacked capacitor cells using a high dielectric constant material as a storage cell dielectric and a combination of conductively doped polysilicon and metal silicide as the capacitor plates of a storage cell for use in high-density dynamic random access memory (DRAM) arrays. The present invention teaches how to fabricate three-dimensional stacked capacitors by modifying an existing stacked capacitor fabrication process to construct the three-dimensional stacked capacitor cell incorporating a high dielectric constant material as the cell dielectric that will allow denser storage cell fabrication with minimal increases of overall memory array dimensions. A capacitance gain of 3 to 10× or more over that of a conventional 3-dimensional storage cell is gained by using a high dielectric constant material as the storage cell dielectric.

We claim: 
     
       1. A process for fabricating a DRAM array on a silicon substrate, said process comprising the following sequence of steps: a) creating a plurality of separately isolated active areas arranged in parallel rows and parallel columns;   b) creating a gate dielectric layer on top of each active area;   c) depositing a first conductive layer superjacent surface of said array;   d) depositing a first dielectric layer superjacent said first conductive layer;   e) masking and etching said first conductive and said first dielectric layers to form a plurality of parallel conductive word lines aligned along said rows such that each said word line passes over an inner portion of each said active area being separated therefrom by a remanent of said gate dielectric layer;   f) creating a conductively-doped digit line junction and storage node junction within each said active area on opposite sides of each said word line;   g) depositing a second dielectric layer superjacent said array surface;   h) creating a first aligned buried contact location at each said digit line junction in each said active area;   i) depositing a second conductive layer superjacent said array surface, said second conductive layer making direct contact to said digit line junctions at said first buried contact locations;   j) depositing a third dielectric layer superjacent to said second conductive layer;   k) masking and etching said second conductive layer and said third dielectric layer to form a plurality of parallel conductive digit lines aligned along said columns such that a digit line makes electrical contact at each digit line junction within a column, said digital lines running perpendicular to and over said word lines forming a 3-dimensional, waveform-shaped topology;   l) depositing a fourth dielectric layer superjacent said array surface;   m) masking and etching a second aligned buried contact location allowing access to an active area and thereby forming vertical sidewalls within opening of said buried contact location;   n) depositing a third conductive layer superjacent said fourth dielectric layer and said second buried contact opening;   o) patterning said third conductive layer to form storage node plates having a v-shaped cross-section, said storage node plates conforming to said 3-dimensional, waveform shaped topology and thereby making contact to said active area at said second buried contact location;   p) depositing a fifth dielectric layer on said storage node plates and etching said fifth dielectric layer to leave to leave a remnant dielectric between the storage node plates of neighboring cells thereby isolating adjacent storage node plates;   q) placing a cell dielectric layer superjacent an exposed upper portion of said storage node plate, said cell dielectric layer conforming to existing waveform shaped topology, said cell dielectric layer is a layer of high dielectric constant material; and   r) depositing a fourth conductive layer superjacent said cell dielectric layer, thereby forming a top cell plate common to the entire memory array.   
     
     
       2. A process as recited in claim 1, wherein said gate dielectric layer is silicon oxide. 
     
     
       3. A process as recited in claim 1, wherein said first and said second buried contacts are self aligned. 
     
     
       4. A process as recited in claim 1, wherein said first, said second, said third and said fourth conductive layers comprise a layer of metal silicide and a layer of conductively-doped polysilicon. 
     
     
       5. A process as recited in claim 4, wherein said metal silicide layer is formed from a metal selected from the group consisting essentially of platinum, chromium, cobalt, chromium, or titanium. 
     
     
       6. A process as recited in claim 1, wherein said first, said second, said third and said fourth dielectric layers are selected from the group consisting essentially of silicon oxide or nitride. 
     
     
       7. A process as recited in claim 1, wherein said first, said second, said third and said fourth dielectric layers are deposited by chemical vapor deposition. 
     
     
       8. A process as recited in claim 1, wherein said high dielectric constant material is selected from the group consisting essentially of Ta 2  O 5 , Y 2  O 3 , ZrO 2 , lead zirconate titanate or PbZr 0 .5 Ti 0 .5 O 3 . 
     
     
       9. A process as recited in claim 1, wherein said fifth dielectric layer is selected from the group consisting essentially of oxide or nitride. 
     
     
       10. A process as recited in claim 1, wherein said high dielectric constant material is a PZT ferroelectric material applied by a sol-gel method. 
     
     
       11. A process for fabricating a DRAM storage capacitor on a silicon substrate having active areas, word lines and digit lines, said process comprising the following sequence of steps: a) depositing a fist dielectric layer on surface of said silicon, said first dielectric layer conforming to existing topology;   b) masking and etching a self aligned buried contact location allowing access to said active area and thereby forming vertical sidewalls within opening of said buried contact location;   c) depositing a first conductive layer superjacent said first dielectric layer and said buried contact opening;   d) patterning said first conductive layer to form storage node plates having a v-shaped cross-section, said storage node plates conforming to said existing topology and thereby making contact to said active area at said buried contact location;   e) depositing a second dielectric layer on said storage node plates and etching said second dielectric layer to leave a remmant dielectric between the storage node plates of neighboring cells thereby isolating adjacent storage node plates;   f) placing a cell dielectric layer superjacent an exposed upper portion of said storage node plates said cell dielectric layer is a layer of high dielectric constant material; and   g) depositing a second conductive layer superjacent said cell dielectric layer, thereby forming a top cell plate common to the entire memory array.   
     
     
       12. A process as claimed in claim 11, wherein said buried contact is self aligned. 
     
     
       13. A process as recited in claim 11, wherein said first and said second conductive layers comprise a layer of metal silicide and a layer of conductively-doped polysilicon. 
     
     
       14. A process as recited in claim 13, wherein said metal silicide layer is formed from a metal selected from the group consisting essentially of platinum, chromium, cobalt, chromium, or titanium. 
     
     
       15. A process as recited in claim 11, wherein said high dielectric constant material is selected from the group consisting essentially of Ta 2  O 5 , Y 2  O 3 , ZrO 2 , lead zirconate titanate or PbZr 0 .5 Ti 0 .5 O 3 . 
     
     
       16. A process as recited in claim 11, wherein said second dielectric layer is selected from the group consisting essentially of silicon oxide or nitride. 
     
     
       17. A process as recited in claim 11, wherein said first dielectric layer is selected from the group consisting essentially of oxide or nitride. 
     
     
       18. A process as recited in claim 11, wherein said first dielectric layer is deposited by chemical vapor deposition. 
     
     
       19. A process as recited in claim 11, wherein said high dielectric constant material is a PZT ferroelectric material applied by a sol-gel method.