Inventor

NIIMI HIROAKI

US127 patents

⚠️ This page may combine multiple inventors who share the name “NIIMI HIROAKI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NIIMI HIROAKI

TEXAS INSTRUMENTS INC

Method for non-thermally nitrided gate formation for high voltage devices

Method of two-step annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile

Temperature spike for uniform nitridization of ultra-thin silicon dioxide layers in transistor gates

Method for uniform nitridization of ultra-thin silicon dioxide layers in transistor gates

Method and system for modifying a gate dielectric stack containing a high-k layer using plasma processing

Method of ammonia annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile

Structure and method for metal gate stack oxygen concentration control using an oxygen diffusion barrier layer and a sacrificial oxygen gettering layer

High-k / metal gate CMOS transistors with TiN gates

Nitridation of STI liner oxide for modulating inverse width effects in semiconductor devices

Method for annealing ultra-thin, high quality gate oxide layers using oxidizer/hydrogen mixtures

Formation of nitrogen containing dielectric layers having a uniform nitrogen distribution therein using a high temperature chemical treatment

Methods to enhance effective work function of mid-gap metal by incorporating oxygen and hydrogen at a low thermal budget

System and method for mitigating oxide growth in a gate dielectric

System and method for mitigating oxide growth in a gate dielectric

Fringe capacitance reduction for replacement gate CMOS

High-k / metal gate CMOS transistors with TiN gates

Structure and method for metal gate stack oxygen concentration control using an oxygen diffusion barrier layer and a sacrificial oxygen gettering layer

Metal-gate MOS transistor and method of forming the transistor with reduced gate-to-source and gate-to-drain overlap capacitance

Reliable high voltage gate dielectric layers using a dual nitridation process

Reliable high voltage gate dielectric layers using a dual nitridation process

IBM

Hybrid source and drain contact formation using metal liner and metal insulator semiconductor contacts

Low resistance source drain contact formation

Forming a contact for a semiconductor device

Dual metal-insulator-semiconductor contact structure and formulation method

Dipole-based contact structure to reduce metal-semiconductor contact resistance in MOSFETs

Hybrid source and drain contact formation using metal liner and metal insulator semiconductor contacts

Dual metal-insulator-semiconductor contact structure and formulation method

CMOS VFET contacts with trench solid and liquid phase epitaxy

Vertical channel field-effect transistor (FET) process compatible long channel transistors

Hybrid source and drain contact formation using metal liner and metal insulator semiconductor contacts

Forming a contact for a semiconductor device

Dual metal-insulator-semiconductor contact structure and formulation method

Contact formation in semiconductor devices

GLOBALFOUNDRIES INC

Complementary FETs with wrap around contacts and method of forming same

Methods of forming replacement gate structures and bottom and top source/drain regions on a vertical transistor device

Method for forming source/drain contacts during CMOS integration using confined epitaxial growth techniques

Complementary FETs with wrap around contacts and methods of forming same

Vertical-transport field-effect transistors with a damascene gate strap

Formation of bottom junction in vertical FET devices

Methods, apparatus and system for forming wrap-around contact with dual silicide

Formation of bottom junction in vertical FET devices

Method for forming source/drain contacts during CMOS integration using confined epitaxial growth techniques and the resulting semiconductor devices

Integration of hybrid germanium and group III-V contact epilayer in CMOS

Methods of forming merged source/drain regions on integrated circuit products

CHAMBERS JAMES JOSEPH

Structure and method for metal gate stack oxygen concentration control using an oxygen diffusion barrier layer and a sacrificial oxygen gettering layer

Structure and method for dual work function metal gate CMOS with selective capping

PANASONIC CORP

RFID tag and RFID tag communication distance modification method

NIIMI HIROAKI

Methods to enhance effective work function of mid-gap metal by incorporating oxygen and hydrogen at a low thermal budget

BEVAN MALCOLM J

System and method for mitigating oxide growth in a gate dielectric

TOKYO ELECTRON LTD

Reverse contact and silicide process for three-dimensional logic devices