Methods to enhance effective work function of mid-gap metal by incorporating oxygen and hydrogen at a low thermal budget

Abstract

A process is disclosed of forming metal replacement gates for PMOS transistors with oxygen in the metal gates such that the PMOS gates have effective work functions above 4.85. Metal work function layers in the PMOS gates are oxidized at low temperature to increase their effective work functions to the desired PMOS range. Hydrogen may also be incorporated at an interface between the metal gates and underlying gate dielectrics. Materials for the metal work function layers and processes for the low temperature oxidation are disclosed.

1. An integrated circuit comprising a PMOS transistor, said PMOS transistor further including:
 a substrate; 
 a PMOS gate dielectric layer formed on a top surface of said substrate; 
 a PMOS gate work function metal layer formed on a top surface of said PMOS gate dielectric layer, such that:
 said PMOS gate work function metal layer includes oxygen atoms such that said oxygen atoms have a distribution of at least 1×10 15  atoms/cm 2  within 1 nanometer of said top surface of said PMOS gate dielectric layer; and 
 said PMOS gate work function metal layer includes oxygen such that an effective work function of said PMOS gate work function metal layer is above 4.85 eV; and 
 
 a PMOS metal fill gate formed over and in direct electrical connection with said PMOS gate work function metal layer. 
 
     
     
       2. The integrated circuit of  claim 1 , in which said PMOS gate work function metal layer is between 1 and 10 nanometers thick. 
     
     
       3. The integrated circuit of  claim 1 , in which said PMOS gate work function metal layer includes a metal selected from the group consisting of:
 TiN, 
 TaN, and 
 TaC. 
 
     
     
       4. The integrated circuit of  claim 1 , wherein said PMOS gate work function metal layer includes hydrogen atoms, deuterium atoms or a combination thereof, such that said hydrogen and deuterium atoms have a distribution of at least 1×10 15  atoms/cm 2  within 1 nanometer of said top surface of said PMOS gate dielectric layer. 
     
     
       5. The integrated circuit of  claim 1 , in which a composition of said PMOS gate dielectric layer is selected from the group consisting of:
 SiO 2 , 
 SiON, 
 Al 2 O 3 , 
 AlON, 
 HfO, 
 HfSiO, 
 HfSiON, 
 ZrO, 
 ZrSiO, 
 ZrSiON, 
 nitridated SiO 2 , 
 nitridated Al 2 O 3 , 
 nitridated HfO, 
 nitridated HfSiO, 
 nitridated ZrO, 
 nitridated ZrSiO, and 
 any combination thereof. 
 
     
     
       6. An integrated circuit comprising a PMOS transistor, said PMOS transistor further including:
 a substrate; 
 a PMOS gate dielectric layer formed on a top surface of said substrate; 
 a PMOS gate work function metal layer formed on a top surface of said PMOS gate dielectric layer, such that:
 said PMOS gate work function metal layer includes oxygen atoms such that said oxygen atoms have an average concentration between 1×10 18  atoms/cm 3  and 1×10 21  atoms/cm 3 ; and 
 said PMOS gate work function metal layer includes oxygen such that an effective work function of said PMOS gate work function metal layer is above 4.85 eV; and 
 
 a PMOS metal fill gate formed over and in direct electrical connection with said PMOS gate work function metal layer. 
 
     
     
       7. The integrated circuit of  claim 6 , in which said PMOS gate work function metal layer is between 1 and 10 nanometers thick. 
     
     
       8. The integrated circuit of  claim 6 , in which said PMOS gate work function metal layer includes a metal selected from the group consisting of:
 TiN, 
 TaN, and 
 TaC. 
 
     
     
       9. The integrated circuit of  claim 6 , wherein said PMOS gate work function metal layer includes hydrogen atoms, deuterium atoms or a combination thereof, such that said hydrogen and deuterium atoms have a distribution of at least 1×10 15  atoms/cm 2  within 1 nanometer of said top surface of said PMOS gate dielectric layer. 
     
     
       10. The integrated circuit of  claim 6 , in which a composition of said PMOS gate dielectric layer is selected from the group consisting of:
 SiO 2 , 
 SiON, 
 Al 2 O 3 , 
 AlON, 
 HfO, 
 HfSiO, 
 HfSiON, 
 ZrO, 
 ZrSiO, 
 ZrSiON, 
 nitridated SiO 2 , 
 nitridated Al 2 O 3 , 
 nitridated HfO, 
 nitridated HfSiO, 
 nitridated ZrO, 
 nitridated ZrSiO, and 
 any combination thereof.