Vertical-transport field-effect transistors with a damascene gate strap

Abstract

Methods for forming a structure that includes vertical-transport field-effect transistors and structures that include vertical-transport field-effect transistors. A first semiconductor fin is separated from a second semiconductor fin by a gap. A gate stack is conformally deposited that extends across the first semiconductor fin, the second semiconductor fin, and the gap. A section of the gate stack is located in the gap. A gate strap layer is formed in the gap on the section of the gate stack. The gate stack is patterned to form a first gate electrode associated with the first semiconductor fin and a second gate electrode associated with the second semiconductor fin. The gate strap layer masks the section of the gate stack when the gate stack is patterned. The first gate electrode is connected with the second gate electrode by the gate strap layer and the section of the gate stack.

What is claimed is: 
     
       1. A method comprising:
 forming a first semiconductor fin; 
 forming a second semiconductor fin separated from the first semiconductor fin by a first gap; 
 conformally depositing a gate stack that extends across the first semiconductor fin, the second semiconductor fin, and the first gap, wherein a first section of the gate stack is located in the first gap; 
 forming a gate strap layer in the first gap on the first section of the gate stack; and 
 patterning the gate stack to form a first gate electrode associated with the first semiconductor fin and a second gate electrode associated with the second semiconductor fin, 
 wherein the gate strap layer masks the first section of the gate stack when the gate stack is patterned, and the first gate electrode is connected with the second gate electrode by the gate strap layer and the first section of the gate stack. 
 
     
     
       2. The method of  claim 1  wherein the first semiconductor fin projects in a vertical direction from a first source/drain region of a first vertical-transport field-effect transistor, and further comprising:
 epitaxially growing a second source/drain region of the first vertical-transport field-effect transistor from the first semiconductor fin, 
 wherein the first gate electrode is arranged in the vertical direction between the first source/drain region and the second source/drain region of the first vertical-transport field-effect transistor. 
 
     
     
       3. The method of  claim 2  wherein the second semiconductor fin projects in the vertical direction from a first source/drain region of a second vertical-transport field-effect transistor, and further comprising:
 epitaxially growing a second source/drain region of the second vertical-transport field-effect transistor from the second semiconductor fin, 
 wherein the second gate electrode is arranged in the vertical direction between the first source/drain region and the second source/drain region of the second vertical-transport field-effect transistor. 
 
     
     
       4. The method of  claim 1  wherein the second semiconductor fin has a sidewall, the first gap is located between an end surface of the first semiconductor fin and an end surface of the second semiconductor fin, and further comprising:
 forming a third semiconductor fin having a sidewall that is separated by a second gap from the sidewall of the second semiconductor fin; and 
 depositing a dielectric layer with a first section that fills the first gap and a second section that fills the second gap. 
 
     
     
       5. The method of  claim 4  further comprising:
 removing the first section of the dielectric layer from the first gap, 
 wherein the gate strap layer is formed in the first gap after the first section of the dielectric layer is removed from the first gap. 
 
     
     
       6. The method of  claim 5  wherein the second section of the dielectric layer is masked by an etch mask when the first section of the dielectric layer is removed from the first gap. 
     
     
       7. The method of  claim 5  wherein patterning the gate stack to form the first gate electrode associated with the first semiconductor fin and the second gate electrode associated with the second semiconductor fin comprises:
 removing the second section of the dielectric layer from the second gap to expose a second section of the gate stack; and 
 removing the second section of the gate stack when the gate stack is patterned to form the first gate electrode and the second gate electrode. 
 
     
     
       8. The method of  claim 7  wherein a third gate electrode associated with the third semiconductor fin is formed when the gate stack is patterned, and the second gap is located between the third gate electrode and the second gate electrode. 
     
     
       9. The method of  claim 1  wherein the first section of the gate stack is positioned on a trench isolation region located between the first semiconductor fin and the second semiconductor fin. 
     
     
       10. The method of  claim 1  wherein the first semiconductor fin and the first gate electrode comprise a first vertical-transport field-effect transistor, the first semiconductor fin projects in a vertical direction from a first source/drain region of the first vertical-transport field-effect transistor, and further comprising:
 forming a second source/drain region of the first vertical-transport field-effect transistor, 
 wherein the first gate electrode is positioned in the vertical direction between the first source/drain region and the second source/drain region of the first vertical-transport field-effect transistor. 
 
     
     
       11. The method of  claim 10  wherein the second semiconductor fin and the second gate electrode comprise a second vertical-transport field-effect transistor, the second semiconductor fin projects in the vertical direction from a first source/drain region of the second vertical-transport field-effect transistor, and further comprising:
 forming a second source/drain region of the second vertical-transport field-effect transistor, 
 wherein the second gate electrode is positioned in the vertical direction between the first source/drain region and the second source/drain region of the second vertical-transport field-effect transistor. 
 
     
     
       12. The method of  claim 11  wherein the first vertical-transport field-effect transistor is an n-type vertical-transport field-effect transistor in which the first source/drain region and the second source/drain region of the first vertical-transport field-effect transistor are comprised of an n-type semiconductor material, and the second vertical-transport field-effect transistor is a p-type vertical-transport field-effect transistor in which the first source/drain region and the second source/drain region of the second vertical-transport field-effect transistor are comprised of a p-type semiconductor material. 
     
     
       13. The method of  claim 1  wherein the first section of the gate stack is located on a trench isolation region in the first gap, and a gate dielectric layer is formed on the first semiconductor fin, the second semiconductor fin, and the trench isolation before the gate stack is conformally deposited. 
     
     
       14. The method of  claim 1  wherein forming the gate strap layer in the first gap on the first section of the gate stack comprises:
 depositing a conductor layer that fills the first gap and that is located on the first semiconductor fin and the second semiconductor fin; and 
 planarizing the conductor layer to remove the conductor layer from the first semiconductor fin and the second semiconductor fin and to form the gate strap layer in the first gap. 
 
     
     
       15. The method of  claim 1  wherein patterning the gate stack to form the first gate electrode associated with the first semiconductor fin and the second gate electrode associated with the second semiconductor fin comprises:
 directionally etching the gate stack to form the first gate electrode and the second gate electrode, 
 wherein the gate stack is directionally etched without an etch mask located on the gate stack. 
 
     
     
       16. The method of  claim 15  wherein the second semiconductor fin has a sidewall, the first gap is located between an end surface of the first semiconductor fin and an end surface of the second semiconductor fin, and further comprising:
 forming a third semiconductor fin with a sidewall that is separated by a second gap from the sidewall of the second semiconductor fin; and 
 depositing a dielectric layer with a first section that fills the first gap and a second section that fills the second gap. 
 
     
     
       17. The method of  claim 16  further comprising:
 removing the first section of the dielectric layer from the first gap before the gate strap layer is formed; and 
 removing the second section of the dielectric layer from the second gap before the gate stack is directionally etched. 
 
     
     
       18. A structure comprising:
 a first vertical-transport field-effect transistor including a first semiconductor fin and a first gate electrode associated with the first semiconductor fin; 
 a second vertical-transport field-effect transistor including a second semiconductor fin and a second gate electrode associated with the first semiconductor fin; and 
 a gate strap layer connecting the first gate electrode with the second gate electrode, 
 wherein the first gate electrode, the second gate electrode, and the gate strap layer have respective side surfaces that are coplanar. 
 
     
     
       19. The structure of  claim 18  wherein the first semiconductor fin and the first gate electrode comprise an n-type vertical-transport field-effect transistor, and the second semiconductor fin and the second gate electrode comprise a p-type vertical-transport field-effect transistor. 
     
     
       20. The structure of  claim 18  wherein the first gate electrode and the second gate electrode are directly connected by the gate strap layer.