Inventor

MCCLURE DAVID CHARLES

US40 patents

⚠️ This page may combine multiple inventors who share the name “MCCLURE DAVID CHARLES”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MCCLURE DAVID CHARLES

ST MICROELECTRONICS INC

Active hierarchical bitline memory architecture

Integrated circuit device having a burn-in mode for which entry into and exit from can be controlled

Circuit and method of fabricating a memory cell for a static random access memory

Integrated circuit output driver

Method and device for acquiring redundancy information from a packaged memory chip

Burn-in stress test mode

Apparatus for testing signal timing and programming delay

Stress test mode

Configurable probe pads to facilitate parallel testing of integrated circuit devices

Method and structure for recovering smaller density memories from larger density memories

Reset initialization

Integrated circuit device having a burn-in mode for which entry into and exit from can be controlled

Edge transition detection circuit with variable impedance delay elements

Edge transition detection circuitry for use with test mode operation of an integrated circuit memory device

Sense amplifier control of a memory device

Method and structure for enhancing the access time of integrated circuit memory devices

Synchronous test mode initialization

Integrated circuit for switching from power supply to battery, integrated latch lock, and associated method for same

Configurable probe pads to facilitate parallel testing of integrated circuit devices

Synchronous test mode initialization

Voltage translating control structure

ESD bonding pad

Method of fabricating a memory cell for a static random access memory

Edge transition detection control of a memory device

Input buffer circuit immune to common mode power supply fluctuations

Method and structure for measurement of a multiple-power-source device during a test mode

Edge transition detection circuitry for use with test mode operation of an integrated circuit memory device

Method and structure for measurement of a multiple-power-source device during a test mode

Reset ramp control

SGS THOMSON MICROELECTRONICS

Method and system for bypassing a faulty line of data or its associated tag of a set associative cache memory

Structure to utilize a partially functional cache memory by invalidation of faulty cache memory locations

Semiconductor memory with multiple clocking for test mode entry

Variable impedance delay elements

Output driver circuitry having a single slew rate resistor

Pipelined chip enable control circuitry and methodology

Synchronous stress test control

Stress test for memory arrays in integrated circuits

Synchronous test mode initalization

External write pulse control method and structure

Pipelined chip enable control circuitry and methodology