Inventor · disambiguated record
Ghavam G. Shahidi
Also filed as: SHAHIDI GHAVAM · SHAHIDI GHAVAM G · SHAHIDI GHAVAM GHAVAMI
377 granted patents·68 pending applications·4,239 citations·filing 1993–2021
99Inventor score
Top patents by PatentIndex Score
445 records- 0199US8906755B1Active matrix using hybrid integrated circuit and bipolar transistorIBM·Filed 2013·Granted Dec 9, 2014·93 cites·8 claims
- 0298US8912020B2Integrating active matrix inorganic light emitting diodes for display devicesBEDELL STEPHEN W·Filed 2011·Granted Dec 16, 2014·47 cites·20 claims
- 0398US8822320B2Dense finFET SRAMIBM·Filed 2012·Granted Sep 2, 2014·38 cites·16 claims
- 0498US8169025B2Strained CMOS device, circuit and method of fabricationBEDELL STEPHEN W·Filed 2010·Granted May 1, 2012·69 cites·24 claims
- 0598US6566177B1Silicon-on-insulator vertical array device trench capacitor DRAMIBM·Filed 1999·Granted May 20, 2003·279 cites·9 claims
- 0698US5784311ATwo-device memory cell on SOI for merged logic and memory applicationsIBM·Filed 1997·Granted Jul 21, 1998·278 cites·10 claims
- 0797US10068529B2Active matrix OLED display with normally-on thin-film transistorsIBM·Filed 2016·Granted Sep 4, 2018·10 cites·18 claims
- 0897US9093533B2FinFET structures having silicon germanium and silicon channelsIBM·Filed 2013·Granted Jul 28, 2015·33 cites·3 claims
- 0997US9064722B2Breakdown voltage multiplying integration schemeBEDELL STEPHEN W·Filed 2012·Granted Jun 23, 2015·27 cites·5 claims
- 1097US8338260B2Raised source/drain structure for enhanced strain coupling from stress linerCHENG KANGGUO·Filed 2010·Granted Dec 25, 2012·25 cites·6 claims
- 1197US8207038B2Stressed Fin-FET devices with low contact resistanceCHENG KANGGUO·Filed 2010·Granted Jun 26, 2012·29 cites·9 claims
- 1297US7968459B2Ion implantation combined with in situ or ex situ heat treatment for improved field effect transistorsIBM·Filed 2008·Granted Jun 28, 2011·104 cites·21 claims
- 1397US7002214B1Ultra-thin body super-steep retrograde well (SSRW) FET devicesIBM·Filed 2004·Granted Feb 21, 2006·160 cites·20 claims
- 1497US6653698B2Integration of dual workfunction metal gate CMOS devicesIBM·Filed 2001·Granted Nov 25, 2003·145 cites·9 claims
- 1597US6333532B1Patterned SOI regions in semiconductor chipsIBM·Filed 1999·Granted Dec 25, 2001·232 cites·27 claims
- 1697US6214694B1Process of making densely patterned silicon-on-insulator (SOI) region on a waferIBM·Filed 1998·Granted Apr 10, 2001·244 cites·17 claims
- 1797US5811857ASilicon-on-insulator body-coupled gated diode for electrostatic discharge (ESD) and analog applicationsIBM·Filed 1996·Granted Sep 22, 1998·167 cites·29 claims
- 1896US9991408B1Monolithically integrated high voltage photovoltaics and light emitting diode with textured surfaceIBM·Filed 2017·Granted Jun 5, 2018·9 cites·5 claims
- 1996US9985164B1Monolithically integrated high voltage photovoltaics and light emitting diode with textured surfaceIBM·Filed 2017·Granted May 29, 2018·9 cites·15 claims
- 2096US9455250B1Distributed decoupling capacitorIBM·Filed 2015·Granted Sep 27, 2016·12 cites·15 claims
- 2196US9293476B2Integrating active matrix inorganic light emitting diodes for display devicesIBM·Filed 2014·Granted Mar 22, 2016·19 cites·13 claims
- 2296US9059016B1Lateral heterojunction bipolar transistorsIBM·Filed 2014·Granted Jun 16, 2015·27 cites·19 claims
- 2396US8022488B2High-performance FETs with embedded stressorsIBM·Filed 2009·Granted Sep 20, 2011·35 cites·14 claims
- 2496US6432754B1Double SOI device with recess etch and epitaxyIBM·Filed 2001·Granted Aug 13, 2002·141 cites·24 claims
- 2595US10090415B1Thin film transistors with epitaxial source/drain contact regionsIBM·Filed 2017·Granted Oct 2, 2018·9 cites·20 claims
- 2695US8642378B1Field-effect inter-digitated back contact photovoltaic deviceIBM·Filed 2012·Granted Feb 4, 2014·10 cites·20 claims
- 2795US8399938B2Stressed Fin-FET devices with low contact resistanceCHENG KANGGUO·Filed 2012·Granted Mar 19, 2013·19 cites·9 claims
- 2895US8169024B2Method of forming extremely thin semiconductor on insulator (ETSOI) device without ion implantationCHENG KANGGUO·Filed 2009·Granted May 1, 2012·33 cites·13 claims
- 2995US8093099B2Lock and key through-via method for wafer level 3D integration and structures producedPURUSHOTHAMAN SAMPATH·Filed 2010·Granted Jan 10, 2012·27 cites·10 claims
- 3095US7365378B2MOSFET structure with ultra-low K spacerIBM·Filed 2005·Granted Apr 29, 2008·32 cites·19 claims
- 3194US8748258B2Method and structure for forming on-chip high quality capacitors with ETSOI transistorsCHENG KANGGUO·Filed 2011·Granted Jun 10, 2014·15 cites·15 claims
- 3294US8513723B2Method and structure for forming high performance MOS capacitor along with fully depleted semiconductor on insulator devices on the same chipBOOTH JR ROGER A·Filed 2010·Granted Aug 20, 2013·20 cites·10 claims
- 3394US8486797B1Bipolar junction transistor with epitaxial contactsHEKMATSHOARTABARI BAHMAN·Filed 2012·Granted Jul 16, 2013·14 cites·25 claims
- 3494US8394710B2Semiconductor devices fabricated by doped material layer as dopant sourceCHENG KANGGUO·Filed 2010·Granted Mar 12, 2013·15 cites·12 claims
- 3594US7855455B2Lock and key through-via method for wafer level 3 D integration and structures producedIBM·Filed 2008·Granted Dec 21, 2010·35 cites·7 claims
- 3694US6855436B2Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion annealIBM·Filed 2003·Granted Feb 15, 2005·50 cites·11 claims
- 3793US10079181B2P-FET with strained silicon-germanium channelIBM·Filed 2017·Granted Sep 18, 2018·6 cites·18 claims
- 3893US9627378B2Methods of forming FINFETs with locally thinned channels from fins having in-situ doped epitaxial claddingIBM·Filed 2015·Granted Apr 18, 2017·7 cites·15 claims
- 3993US9166181B2Hybrid junction field-effect transistor and active matrix structureIBM·Filed 2014·Granted Oct 20, 2015·8 cites·9 claims
- 4093US9018675B2Heterojunction III-V photovoltaic cell fabricationIBM·Filed 2014·Granted Apr 28, 2015·10 cites·7 claims
- 4193US8829339B2Field-effect inter-digitated back contact photovoltaic deviceIBM·Filed 2013·Granted Sep 9, 2014·8 cites·8 claims
- 4293US8574970B2Method of forming an extremely thin semiconductor insulator (ETSOI) FET having a stair-shaped raised source/drainCHENG KANGGUO·Filed 2010·Granted Nov 5, 2013·16 cites·9 claims
- 4392US11094842B2Heterojunction photovoltaic device and fabrication methodIBM·Filed 2019·Granted Aug 17, 2021·2 cites·17 claims
- 4492US9337196B2III-V FinFET CMOS with III-V and germanium-containing channel closely spacedIBM·Filed 2014·Granted May 10, 2016·10 cites·10 claims
- 4592US9269589B2Dense finFET SRAMGLOBALFOUNDRIES US 2 LLC·Filed 2015·Granted Feb 23, 2016·6 cites·20 claims
- 4692US9093548B2Thin film hybrid junction field effect transistorIBM·Filed 2013·Granted Jul 28, 2015·13 cites·18 claims
- 4792US9059212B2Back-end transistors with highly doped low-temperature contactsIBM·Filed 2012·Granted Jun 16, 2015·9 cites·9 claims
- 4892US8940569B2Dual-gate bio/chem sensorIBM·Filed 2012·Granted Jan 27, 2015·12 cites·14 claims
- 4992US8927312B2Method of fabricating MEMS transistors on far back end of lineIBM·Filed 2012·Granted Jan 6, 2015·10 cites·16 claims
- 5092US8815684B2Bulk finFET with super steep retrograde wellIBM·Filed 2012·Granted Aug 26, 2014·12 cites·25 claims
Showing the top 50 of 445 patent records by PatentIndex Score.
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