Inventor

BAO XINYU

US71 patents

⚠️ This page may combine multiple inventors who share the name “BAO XINYU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BAO XINYU

TAIWAN SEMICONDUCTOR MFG CO LTD

Memory device

Memory devices with selector layer and methods of forming the same

Selector-based random number generator and method thereof

Semiconductor package having an encapsulant comprising conductive fillers and method of manufacture

Semiconductor device and method of forming the same

Magnetic memory device and manufacturing method thereof

Operating method, memory system, and control circuit

Memory device and manufacturing method thereof

Methods of writing and forming memory device

Memory devices and methods of forming the same

Memory devices with selector layer and methods of forming the same

Semiconductor device and manufacturing method thereof

Semiconductor device and manufacturing method thereof

Operation methods for ovonic threshold selector, memory device and memory array

Memory devices and methods of forming the same

Memory devices with selector layer and methods of forming the same

Semiconductor device and manufacturing method thereof

Selector-based random number generator and method thereof

Memory device, method of forming the same, and memory array

Memory selector threshold voltage recovery

First fire operation for ovonic threshold switch selector

Semiconductor package having an encapulant comprising conductive fillers and method of manufacture

Memory selector threshold voltage recovery

First fire operation for ovonic threshold switch selector

Adjusting operation voltage of cross point memory according to aging information

Cross-point memory-selector composite pillar stack structures and methods of forming the same

APPLIED MATERIALS INC

Selective process for source and drain formation

Methods for bottom up fin structure formation

Integrated system and method for source/drain engineering

Selective process for source and drain formation

Method for wafer outgassing control

Method of epitaxial growth shape control for CMOS applications

Method and apparatus for wafer outgassing control

Integrated method for wafer outgassing reduction

Method of forming structures with V shaped bottom on silicon substrate

Method and solution for cleaning InGaAs (or III-V) substrates

Method for removing native oxide and residue from a III-V group containing surface

Self-aligned EPI contact flow

Structure and method of forming metamorphic heteroepi materials and III-V channel structures on si

Integrated system for semiconductor process

Method of uniform channel formation

Multi-level injector with angled gas outlet for semiconductor epitaxy growth

Method of utilizing a degassing chamber to reduce arsenic outgassing following deposition of arsenic-containing material on a substrate

Methods for bottom up fin structure formation

Method for removing native oxide and residue from a III-V group containing surface

Co-doping process for n-MOS source drain application

WANG DELI

Vertical group III-V nanowires on si, heterostructures, flexible arrays and fabrication

Nanowire array-based light emitting diodes and lasers

BAO XINYU

Method for forming group III/V conformal layers on silicon substrates

LAM RES CORP

Atomic layer treatment process using metastable activated radical species