Memory devices and methods of forming the same

Abstract

A memory device includes a substrate, a transistor disposed over the substrate, an interconnect structure disposed over and electrically connected to the transistor, and a memory stack disposed between two adjacent metallization layers of the interconnect structure. The memory stack includes a bottom electrode disposed over the substrate and electrically connected to a bit line, a memory layer disposed over the bottom electrode, a selector layer disposed over the memory layer, and a top electrode disposed over the selector layer and electrically connected to a word line. Besides, at least one moisture-resistant layer is provided adjacent to and in physical contact with the selector layer, and the at least one moisture-resistant layer includes an amorphous material.

What is claimed is: 
     
       1. A memory device, comprising:
 a substrate; 
 a transistor disposed over the substrate; 
 an interconnect structure disposed over and electrically connected to the transistor; and 
 a memory stack disposed between two adjacent metallization layers of the interconnect structure and comprising:
 a bottom electrode disposed over the substrate and electrically connected to a bit line; 
 a memory layer disposed over the bottom electrode; 
 a selector layer disposed over the memory layer; and 
 a top electrode disposed over the selector layer and electrically connected to a word line, 
 wherein at least one moisture-resistant layer is provided adjacent to and in contact with the selector layer, the at least one moisture-resistant layer comprises an amorphous material. 
 
 
     
     
       2. The memory device of  claim 1 , wherein the at least one moisture-resistant layer comprises GeCTe, CTe, GeSe, BCTe, SiGeCTe, SiCTe, or a combination thereof. 
     
     
       3. The memory device of  claim 1 , wherein the selector layer comprises a composition of the at least one moisture-resistant layer and further comprises a nitrogen element. 
     
     
       4. The memory device of  claim 1 , wherein the at least one moisture-resistant layer comprises an oxygen concentration of about 5 at % or less. 
     
     
       5. The memory device of  claim 1 , wherein one of the at least one moisture-resistant layer is provided between the selector layer and the top electrode. 
     
     
       6. The memory device of  claim 1 , wherein one of the at least one moisture-resistant layer is provided between the selector layer and the memory layer. 
     
     
       7. The memory device of  claim 1 , further comprising a humidity blocking wherein one of the at least one moisture-resistant layer disposed is provided on a sidewall of the selector layer and a sidewall of the memory layer. 
     
     
       8. The memory device of  claim 1 , wherein a thickness ratio of the moisture-resistant layer to the selector layer ranges from about 1:3 to 1:10. 
     
     
       9. The memory device of  claim 1 , wherein a width of the bottom electrode is less than a width of the top electrode. 
     
     
       10. The memory device of  claim 1 , wherein a width of the bottom electrode is greater than a width of the top electrode. 
     
     
       11. A memory device, comprising:
 a substrate; 
 a transistor disposed over the substrate; 
 an interconnect structure disposed over and electrically connected to the transistor; and 
 a memory stack disposed between two adjacent metallization layers of the interconnect structure and comprising:
 a bottom electrode disposed over the substrate and serving as a bit line extending in a first direction; 
 a top electrode disposed over the bottom electrode and serving as a word line extending in a second direction different from the first direction; and 
 a selector structure and a memory layer provided between the bottom electrode and the top electrode, 
 wherein the selector structure comprises a first material and at least one second material in direct contact with each other, the first material is a nitrogen-containing layer, and the at least one second material is a nitrogen-free layer. 
 
 
     
     
       12. The memory device of  claim 11 , wherein the first material comprises NGeCTe, NSiGeCTe, NSiCTe, NSeGeCTe, NSiSeCTe, NSeCTe, NBCTe, NSiBCTe, NGeBCTe, or a combination thereof. 
     
     
       13. The memory device of  claim 11 , wherein the at least one second material comprises GeCTe, CTe, GeSe, BCTe, SiGeCTe, SiCTe, or a combination thereof. 
     
     
       14. The memory device of  claim 11 , wherein the second material is in contact with the top electrode. 
     
     
       15. The memory device of  claim 11 , wherein the at least one second material comprises a lower second material and an upper second material, and the first material is inserted between the lower second material and the upper second material. 
     
     
       16. The memory device of  claim 15 , wherein a thickness of the upper second material is different from a thickness of the lower second material. 
     
     
       17. The memory device of  claim 15 , wherein a thickness of the upper second material is substantially equal to a thickness of the lower second material. 
     
     
       18. A method of forming a memory device, comprising:
 providing a substrate having a transistor thereon; 
 forming an interconnect structure over and electrically connected to the transistor; and 
 forming a memory stack disposed between two adjacent metallization layers of the interconnect structure, wherein the memory stack comprises:
 a bottom electrode disposed over the substrate and serving as a bit line extending in a first direction; 
 a top electrode disposed over the bottom electrode and serving as a word line extending in a second direction different from the first direction; and 
 a selector structure and a memory layer provided between the bottom electrode and the top electrode, 
 wherein the selector structure comprises a first material and at least one second material in direct contact with each other, the first material is a nitrogen-containing layer, and the at least one second material is a nitrogen-free layer. 
 
 
     
     
       19. The method of  claim 18 , further comprising forming a blocking layer on a sidewall of the memory stack. 
     
     
       20. The method of  claim 18 , wherein the first material comprises NGeCTe, NSiGeCTe, NSiCTe, NSeGeCTe, NSiSeCTe, NSeCTe, NBCTe, NSiBCTe, NGeBCTe, or a combination thereof.