Inventor
SHOBHA HOSADURGA
US84 patents
⚠️ This page may combine multiple inventors who share the name “SHOBHA HOSADURGA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
42 patentsUS10529622B1Jan 7, 2020
Void-free metallic interconnect structures with self-formed diffusion barrier layers
IBM16 citations94
US10020255B1Jul 10, 2018
Integration of super via structure in BEOL
IBM36 citations94
US10020254B1Jul 10, 2018
Integration of super via structure in BEOL
IBM39 citations94
US9685406B1Jun 20, 2017
Selective and non-selective barrier layer wet removal
IBM34 citations94
US8927442B1Jan 6, 2015
SiCOH hardmask with graded transition layers
IBM33 citations92
US7737052B2Jun 15, 2010
Advanced multilayer dielectric cap with improved mechanical and electrical properties
IBM21 citations92
US6919420B2Jul 19, 2005
Acid-cleavable acetal and ketal based epoxy oligomers
IBM21 citations91
US11152257B2Oct 19, 2021
Barrier-less prefilled via formation
IBM5 citations84
US10002831B2Jun 19, 2018
Selective and non-selective barrier layer wet removal
IBM7 citations84
US9806023B1Oct 31, 2017
Selective and non-selective barrier layer wet removal
IBM8 citations84
US9312224B1Apr 12, 2016
Interconnect structure containing a porous low k interconnect dielectric/dielectric cap
IBM9 citations84
US8383507B2Feb 26, 2013
Method for fabricating air gap interconnect structures
IBM8 citations84
US7750479B2Jul 6, 2010
Treatment of plasma damaged layer for critical dimension retention, pore sealing and repair
IBM11 citations84
US7776993B2Aug 17, 2010
Underfilling with acid-cleavable acetal and ketal epoxy oligomers
IBM8 citations82
US11756887B2Sep 12, 2023
Backside floating metal for increased capacitance
IBM5 citations75
US11101175B2Aug 24, 2021
Tall trenches for via chamferless and self forming barrier
IBM2 citations73
US11056426B2Jul 6, 2021
Metallization interconnect structure formation
IBM6 citations73
US10763160B1Sep 1, 2020
Semiconductor device with selective insulator for improved capacitance
IBM5 citations73
US10529662B2Jan 7, 2020
Method and structure to construct cylindrical interconnects to reduce resistance
IBM3 citations73
US10361117B2Jul 23, 2019
Selective ILD deposition for fully aligned via with airgap
IBM1 citations73
US9735005B1Aug 15, 2017
Robust high performance low hydrogen silicon carbon nitride (SiCNH) dielectrics for nano electronic devices
IBM2 citations73
US9558934B2Jan 31, 2017
Hydrogen-free silicon-based deposited dielectric films for nano device fabrication
IBM3 citations73
US12538553B2Jan 27, 2026
Contact structure for power delivery on semiconductor device
IBM1 citations64
US12424549B2Sep 23, 2025
Skip-level TSV with hybrid dielectric scheme for backside power delivery
IBM1 citations64
US12550713B2Feb 10, 2026
Hybrid buried power rail structure with dual front side and backside processing
IBM0 citations63
US12424557B2Sep 23, 2025
Dual structured buried rail
IBM0 citations63
US12417963B2Sep 16, 2025
Isolation rail between backside power rails
IBM0 citations63
US12412836B2Sep 9, 2025
Backside power plane
IBM0 citations63
US12334442B2Jun 17, 2025
Dielectric caps for power and signal line routing
IBM0 citations63
US12261056B2Mar 25, 2025
Top via patterning using metal as hard mask and via conductor
IBM0 citations63
US11621189B2Apr 4, 2023
Barrier-less prefilled via formation
IBM0 citations63
US11315827B2Apr 26, 2022
Skip via connection between metallization levels
IBM0 citations63
US10943866B2Mar 9, 2021
Method and structure to construct cylindrical interconnects to reduce resistance
IBM0 citations63
US10679892B1Jun 9, 2020
Multi-buried ULK field in BEOL structure
IBM1 citations63
US8373271B2Feb 12, 2013
Interconnect structure with an oxygen-doped SiC antireflective coating and method of fabrication
IBM4 citations63
US8362596B2Jan 29, 2013
Engineered interconnect dielectric caps having compressive stress and interconnect structures containing same
IBM4 citations63
US8354703B2Jan 15, 2013
Semiconductor capacitor
IBM3 citations63
US12588261B2Mar 24, 2026
Selective deposition on metals using porous low-k materials
IBM0 citations62
US12266607B2Apr 1, 2025
Bottom barrier free interconnects without voids
IBM0 citations62
US11177169B2Nov 16, 2021
Interconnects with gouged vias
IBM0 citations62
US11164815B2Nov 2, 2021
Bottom barrier free interconnects without voids
IBM0 citations62
US10903116B2Jan 26, 2021
Void-free metallic interconnect structures with self-formed diffusion barrier layers
IBM0 citations62
NGUYEN SON VAN
2 patentsTESSERA LLC
2 patentsCHANDA KAUSHIK
1 patentLIN QINGHUANG
1 patentADEIA SEMICONDUCTOR SOLUTIONS LLC
1 patentTESSERA INC
1 patentShowing the top 50 of 84 patents by PatentIndex Score.