Inventor

PAWLOWSKI STEPHEN S

US56 patents

⚠️ This page may combine multiple inventors who share the name “PAWLOWSKI STEPHEN S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PAWLOWSKI STEPHEN S

INTEL CORP

Quad pumped bus architecture and protocol

Queue ordering for memory and I/O transactions in a multiple concurrent transaction computer system

Method and apparatus for performing deferred transactions

Quad pumped bus architecture and protocol

Method and apparatus for hazard detection and distraction avoidance for a vehicle

Method and apparatus for performing TLB shutdown operations in a multiprocessor system without invoking interrup handler routines

Highly pipelined bus architecture

Method and apparatus for tracking transactions in a pipelined bus

Method and apparatus for performing deferred transactions

Multi-processor system for selecting a processor which has successfully written it&#39;s ID into write-once register after system reset as the boot-strap processor

Dynamic discovery of wireless peripherals

Enhanced highly pipelined bus architecture

Snoop phase in a highly pipelined bus architecture

Quad pumped bus architecture and protocol

Response and data phases in a highly pipelined bus architecture

Mechanisms for converting interrupt request signals on address and data lines to interrupt message signals

Method and apparatus for responding to unclaimed bus transactions

Scalable, high bandwidth multicard memory system utilizing a single memory controller

Mechanisms for converting interrupt request signals on address and data lines to interrupt message signals

Method and apparatus for ordering writeback data transfers on a bus

Method and apparatus for changing data transfer widths in a computer system

Computer memory subsystem and method for performing opportunistic write data transfers during an access latency period within a read or refresh operation

System and apparatus including lowest priority logic to select a processor to receive an interrupt message

Apparatus for reducing asynchronous service latency in a time slot-based memory arbitration scheme

Method for minimizing CPU memory latency while transferring streaming data

Method and apparatus for controlling data transfers between a bus and a memory device using a multi-chip memory controller

Asynchronous modular bus architecture with cache consistency

Transactions supporting interrupt destination redirection and level triggered interrupt semantics

Method and apparatus for switching between source-synchronous and common clock data transfer modes in a multiple processing system

Method and apparatus for source synchronous data transfer

Method and apparatus for dynamically controlling bus access from a bus agent based on bus pipeline depth

Data flow control mechanism for a bus supporting two-and three-agent transactions

Method and apparatus for conducting bus transactions between two clock independent bus agents of a computer system using a transaction by transaction deterministic request/response protocol and burst transfer

Method and mechanism for virtualizing legacy sideband signals in a hub interface architecture

Mechanisms for converting interrupt request signals on address and data lines to interrupt message signals

High bandwidth self-timed data clocking scheme for memory bus implementation

Memory system including a memory controller having a data strobe generator and method for accesing a memory using a data storage

Computer system formed with a processor and a system board provided with complementary initialization support

Method and apparatus for supporting multiple overlapping address spaces on a shared bus

Method and apparatus for supporting multiple overlapping address spaces on a shared bus

Filter micro-coded accelerator

MICRON TECHNOLOGY INC

Memory device protection using interleaved multibit symbols

Memory apparatus for providing reliability, availability, and serviceability

Memory device protection using interleaved multibit symbols

Memory controller architecture

Cache bypass

Extended line width memory-side cache systems and methods

Adaptive line width cache systems and methods

INTEL CORPORTION

Apparatus for memory resource arbitration based on dedicated time slot allocation

BELL DENNIS M

Peripheral protocol negotiation

Multi-processor system for selecting a processor which has successfully written it's ID into write-once register after system reset as the boot-strap processor