Inventor
TURNER ANDREW A
US18 patents
⚠️ This page may combine multiple inventors who share the name “TURNER ANDREW A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
15 patentsUS9588177B1Mar 7, 2017
Optimizing generation of test configurations for built-in self-testing
IBM17 citations81
US10101388B2Oct 16, 2018
Method for enhanced semiconductor product diagnostic fail signature detection
IBM2 citations70
US9087841B2Jul 21, 2015
Self-correcting power grid for semiconductor structures method
IBM2 citations60
US11989071B2May 21, 2024
Dynamic guard band with timing protection and with performance protection
IBM1 citations58
US9733307B1Aug 15, 2017
Optimized chain diagnostic fail isolation
IBM1 citations51
US9712112B1Jul 18, 2017
Dynamic noise mitigation in integrated circuit devices using local clock buffers
IBM1 citations51
US8860113B2Oct 14, 2014
Creating deep trenches on underlying substrate
IBM0 citations51
US9214427B2Dec 15, 2015
Method of self-correcting power grid for semiconductor structures
IBM0 citations50
US10215804B2Feb 26, 2019
Semiconductor power and performance optimization
IBM0 citations49
US11953982B2Apr 9, 2024
Dynamic guard band with timing protection and with performance protection
IBM0 citations47
US11169841B2Nov 9, 2021
Tunable power save loop for processor chips
IBM0 citations46
US10768226B2Sep 8, 2020
Testing mechanism for a proximity fail probability of defects across integrated chips
IBM0 citations46
US10114071B2Oct 30, 2018
Testing mechanism for a proximity fail probability of defects across integrated chips
IBM0 citations46
US9557381B1Jan 31, 2017
Physically aware insertion of diagnostic circuit elements
IBM0 citations40
US9921264B2Mar 20, 2018
Method and apparatus for offline supported adaptive testing
IBM0 citations30