Testing mechanism for a proximity fail probability of defects across integrated chips

Abstract

According to an embodiment, a testing mechanism determines a status of circuits within a chip by analyzing fail signatures on a by-level basis to identify a high probability defect area within the chip. The testing mechanism further determines a whether functionally needed circuitry of the chip intersects with the high probability defect area within the chip and determines the status of the circuits in response to the determining of whether the functionally needed circuitry intersects with the high probability defect area.

What is claimed is: 
     
       1. A processor-implemented method implementing a testing mechanism for determining a status of circuitry within a chip, the chip comprising a semiconductor wafer including one or more levels on which one or more resistors, one or more capacitors, and one or more transistors are fabricated to provide the circuitry, each of the one or more levels being a structural portion of the chip itself, the processor-implemented method comprising:
 collecting, by the testing mechanism, fail signatures from portions of the circuitry within the chip to determine the status of the circuitry within a chip, where the fail signatures evidence lack of operability for the portions of the circuitry within the chip; 
 analyzing, by the testing mechanism, the fail signatures on a by-level basis to produce analyzed signatures; 
 statistically, by the testing mechanism, determining by-level fail probabilities and associated confidence scores utilizing tracing diagnostics of the fail signatures, the by-level fail probabilities comprise statistical determinations that the portions of the circuitry within the chip contain defects and that the portions of the circuitry within the chip are likely to fail due to those defects, the by-level fail probabilities being statistically determined based on a plurality of signal types received as the tracing diagnostics by the testing mechanism during testing of the chip, the confidence scores comprising an agreement level between multiple by-level fail probabilities; 
 determining, by the testing mechanism, whether functionally needed circuitry of the chip intersects with the high probability defect area within the chip; 
 identifying, by the testing mechanism, at least one high probability defect area within the chip based on the by-level fail probabilities, associated confidence scores, and the analyzed signatures; and 
 determining, by the testing mechanism, the status of the circuitry in response to the determining of whether the functionally needed circuitry intersects with the at least one high probability defect area; and 
 determining, by the testing mechanism, whether to mitigate the at least one high probability defect area when the functionally needed circuitry intersects with the high probability defect area, mitigating the at least one high probability defect area includes blocking operations by turning off corresponding circuitry, thereby preventing use within the chip. 
 
     
     
       2. The processor-implemented method of  claim 1 , the analyzing of the fail signatures further comprising:
 determining the chip to be a bad chip with respect to whether the fail signatures indicate the status of the circuitry to be bad. 
 
     
     
       3. The processor-implemented method of  claim 1 , wherein the high probability defect area comprises a defect and a disposition of near-by circuits. 
     
     
       4. The processor-implemented method of  claim 1 , wherein the status of the circuitry is determined as a bad status if the high probability defect area cannot be mitigated. 
     
     
       5. The processor-implemented method of  claim 1 , wherein the status of the circuitry is determined as a defective status if the at least one high probability defect area can be mitigated. 
     
     
       6. The processor-implemented method of  claim 1 , wherein the testing mechanism determines the status of the circuitry as a good status when the functionally needed circuitry does not intersect with the at least one high probability defect area. 
     
     
       7. A computer program product comprising a non-transitory computer readable storage medium having program instructions embodied therewith, the program instructions for implementing a testing mechanism for determining a status of circuitry within a chip, the chip comprising a semiconductor wafer including one or more levels on which one or more resistors, one or more capacitors, and one or more transistors are fabricated to provide the circuitry, each of the one or more levels being a structural portion of the chip itself, the testing mechanism of the program instructions executable by a processor to cause the processor to perform:
 collecting fail signatures from portions of the circuitry within the chip to determine the status of the circuitry within a chip, where the fail signatures evidence lack of operability for the portions of the circuitry within the chip; 
 analyzing the fail signatures on a by-level basis to produce analyzed signatures; 
 statistically determining by-level fail probabilities and associated confidence scores utilizing tracing diagnostics of the fail signatures, the by-level fail probabilities comprise that the portions of the circuitry within the chip contain defects and that the portions of the circuitry within the chip are likely to fail due to those defects, the by-level fail probabilities being statistically determined based on a plurality of signal types received as the tracing diagnostics by the testing mechanism during testing of the chip, the confidence scores comprising an agreement level between multiple by-level fail probabilities; 
 determining whether functionally needed circuitry of the chip intersects with the high probability defect area within the chip; 
 identifying at least one high probability defect area within the chip based on the by-level fail probabilities, associated confidence scores, and the analyzed signatures; and 
 determining the status of the circuitry in response to the determining of whether the functionally needed circuitry intersects with the at least one high probability defect area; and 
 determining, by the testing mechanism, whether to mitigate the at least one high probability defect area when the functionally needed circuitry intersects with the high probability defect area, mitigating the at least one high probability defect area includes blocking operations by turning off corresponding circuitry, thereby preventing use within the chip. 
 
     
     
       8. The computer program product of  claim 7 , wherein the program instructions with respect to the analyzing of the fail signatures are further executable by the processor to cause:
 determining the chip to be a bad chip with respect to whether the fail signatures indicate the status of the circuitry to be bad. 
 
     
     
       9. The computer program product of  claim 7 , wherein the at least one high probability defect area comprises a defect and a disposition of near-by circuits. 
     
     
       10. The computer program product of  claim 7 , wherein the testing mechanism determines the status of the circuitry as a good status when the functionally needed circuitry does not intersect with the at least one high probability defect area. 
     
     
       11. A system comprising a processor and a memory storing program instructions thereon, the program instructions for implementing a testing mechanism for determining a status of circuitry within a chip, the chip comprising a semiconductor wafer including one or more levels on which one or more resistors, one or more capacitors, and one or more transistors are fabricated to provide the circuitry, each of the one or more levels being a structural portion of the chip itself, the testing mechanism of the program instructions executable by a processor to cause the system to perform:
 collecting fail signatures from portions of the circuitry within the chip to determine the status of the circuitry within a chip, where the fail signatures evidence lack of operability for the portions of the circuitry within the chip; 
 analyzing the fail signatures on a by-level basis to produce analyzed signatures; 
 statistically determining by-level fail probabilities and associated confidence scores utilizing tracing diagnostics of the fail signatures, the by-level fail probabilities comprise that the portions of the circuitry within the chip contain defects and that the portions of the circuitry within the chip are likely to fail due to those defects, the by-level fail probabilities being statistically determined based on a plurality of signal types received as the tracing diagnostics by the testing mechanism during testing of the chip, the confidence scores comprising an agreement level between multiple by-level fail probabilities; 
 determining whether functionally needed circuitry of the chip intersects with the high probability defect area within the chip; 
 identifying at least one high probability defect area within the chip based on the by-level fail probabilities, associated confidence scores, and the analyzed signatures; and 
 determining the status of the circuitry in response to the determining of whether the functionally needed circuitry intersects with the at least one high probability defect area; and 
 determining whether to mitigate the at least one high probability defect area when the functionally needed circuitry intersects with the high probability defect area, mitigating the at least one high probability defect area includes blocking operations by turning off corresponding circuitry, thereby preventing use within the chip. 
 
     
     
       12. The system of  claim 11 , wherein the program instructions with respect to the analyzing of the fail signatures are further executable by the processor to cause:
 determining the chip to be a bad chip with respect to whether the fail signatures indicate the status of the circuitry to be bad. 
 
     
     
       13. The system of  claim 11 , wherein the at least one high probability defect area comprises a defect and a disposition of near-by circuits.